Invention Grant
- Patent Title: Synchronization circuit for parallel processing
- Patent Title (中): 并行处理同步电路
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Application No.: US871584Application Date: 1992-04-20
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Publication No.: US5192882APublication Date: 1993-03-09
- Inventor: G. Jack Lipovski
- Applicant: G. Jack Lipovski
- Applicant Address: TX Austin
- Assignee: Board of Regents, The University of Texas System
- Current Assignee: Board of Regents, The University of Texas System
- Current Assignee Address: TX Austin
- Main IPC: G06F7/50
- IPC: G06F7/50 ; G06F7/505 ; G06F15/80 ; H03K19/173
Abstract:
An apparatus and method for synchronizing parallel processors utilizing a lookahead synchronization circuit is provided by the present invention. A five gate logic circuit is formed as a cell and this cell can serve as a node in a tree logic operation circuit. The tree is capable of realizing a variety of fetch-and-operation, priority and operation-and-broadcast primitives and the cell can serve in a carry circuit of a binary adder. The tree may be pruned at any point and the circuit will continue to function for those nodes remaining in the tree. Processing elements are attached to leaf nodes of the tree. The present invention is capable of realizing the fetch-and-exclusive-OR, fetch-and-add, fetch-and-AND, fetch-and-OR, fixed priority schema, round-robin priority schema, hogging priority schema, swap, data exchange, broadcast, shift-function, broadcast-from-the-root, AND-and-broadcast, OR-and-broadcast, minimum-and-broadcast, maximum-and-broadcast, exclusive-OR-and-broadcast, fetch-and-minimum, and fetch-and-maximum primitives. The circuit affords significant power in synchronizing parallel processors utilizing simple cells configured in a tree structure.
Public/Granted literature
- US5939083A Nongreasy/nonsticky fatty cosmetic/dermatological compositions Public/Granted day:1999-08-17
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