A delta-sigma modulator for a digital-to-analog converter includes a single adder (60) that has one input thereof multiplexed by multiplexer (62). Four shift registers (64), (66), (68) and (70) are connected in a serial fashion such that the data output by the adder (60) is input to the shift register (64) and the other input of adder (60) is connected to the output of register (70). In operation, the multiplexer (62) first selects the input data for input to the one input of adder (60) and selects the output of register (70) for the other input. This represents the first stage of integration wherein the accumulated value from a previous cycle is added to the present data. The output of the first stage of integration will be cycled through the registers for each overall cycle of the delta-sigma modulator. In the second stage of integration on the next clock cycle of the 4.times. clock, the multiplexer (62) selects the output of the register (68) for adding to the output of the register (70). This represents the operation of the second stage of integration. The output of register (64) represents the output of each stage of integration after the accumulation step, which is then input to one of four shift left registers (82)-(88), which performs a gain scaling function. An overflow condition is also accommodated with an exclusive-OR gate (78).