利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

1139 条记录 (耗时 0.025 秒)

    Delta-sigma modulator, electronic device, and method for controlling delta-sigma modulator
    1.
    发明授权
    Delta-sigma modulator, electronic device, and method for controlling delta-sigma modulator 有权

    公开(公告)号：US10659074B2

    公开(公告)日：2020-05-19

    申请号：US16337201

    申请日：2017-09-01

    申请人： SONY SEMICONDUCTOR SOLUTIONS CORPORATION

    发明人： Eiichi Nakamoto

    IPC分类号： H03M3/00 ,  H03M3/02 ,  H04R3/00

    摘要： To effectively suppress an idle tone in a delta-sigma modulator that generates a feedback signal by a digital-to-analog converter. A filter integrates a difference between an input analog signal and a feedback signal, and outputs the integrated difference as an integrated signal. A preceding-stage quantizer quantizes an integrated signal into a digital signal, and outputs the resulting digital signal as a preceding-stage output signal. An adder adds a predetermined dithering signal to a preceding-stage output signal, and outputs the resulting signal as a subsequent-stage input signal. A subsequent-stage quantizer configured to quantize the subsequent-stage input signal into a digital signal of a shorter number of bits than a preceding-stage output signal, and outputs the resulting digital signal as a subsequent-stage output signal. A digital-to-analog converter configured to convert a subsequent-stage output signal into an analog signal, and outputs the resulting analog signal to a filter as a feedback signal.

    A/D converter
    2.
    发明授权
    A/D converter 有权

    公开(公告)号：US10581452B2

    公开(公告)日：2020-03-03

    申请号：US16196273

    申请日：2018-11-20

    申请人： DENSO CORPORATION

    发明人： Tomohiro Nezuka

    IPC分类号： H03M3/00 ,  H03M1/14 ,  H03M3/02 ,  H03M1/12

    摘要： An A/D converter includes: an integrator circuit executing ΔΣ modulation to an analog signal to be converted; an adder outputting an addition result of at least an output signal of the integrator circuit and a first reference signal as a reference signal of ΔΣ modulation; a quantizer receives an output signal of the integrator circuit, an output signal of the adder, and a second reference signal as a reference signal in cyclic A/D conversion to generate a result of quantization of the output signal of the integrator circuit and the output signal of the adder; and a controller is configured to switch between a ΔΣ modulation mode and a cyclic mode.

    Frequency to current circuit
    5.
    发明授权
    Frequency to current circuit 有权

    公开(公告)号：US10161974B1

    公开(公告)日：2018-12-25

    申请号：US15943487

    申请日：2018-04-02

    申请人： Cadence Design Systems, Inc.

    发明人： Ling Chen ,  Fuyue Wang ,  Thomas Evan Wilson ,  Jianyun Zhang ,  Eric Harris Naviasky

    IPC分类号： G01R23/09 ,  G01R19/00 ,  H03M3/02 ,  H03K7/06

    摘要： Aspects of the present disclosure include a frequency-to-current (F2I) circuit and systems, methods, devices, and other circuits related thereto. The F2I circuit is implemented with a delta-modulator-based control loop to settle and maintain an operating point on a bias node. The control loop provides an integral of an output of a comparator, and the comparator compares it to a self-built voltage reference. Upon powering on the circuit, an integrator in the control loop starts to integrate the charge on both a bias voltage and an internal voltage to provide a settling process for the internal voltage to approximate the reference voltage and for the bias voltage to approximate a predetermined operating point of the bias node. After the circuit has settled, the comparator's output charge toggles and the internal voltage and bias voltage become sawtooth-like waveforms at the reference voltage and operating points, respectively.

    Data communication
    8.
    发明授权
    Data communication 有权

    公开(公告)号：US10003695B2

    公开(公告)日：2018-06-19

    申请号：US15300918

    申请日：2015-03-30

    申请人： BRITISH TELECOMMUNICATIONS PUBLIC LIMITED COMPANY

    发明人： Ian E Horsley ,  Trevor P Linney

    IPC分类号： H03M3/02 ,  H04M11/06 ,  H04L12/26 ,  H04L12/811 ,  H04L5/00 ,  H04L12/64

    CPC分类号： H04M11/062 ,  H04L5/0007 ,  H04L43/08 ,  H04L47/38 ,  H04L2012/6478 ,  Y02D50/44

    摘要： A method of controlling a digital subscriber line (DSL) transceiver for use in transferring data over a DSL connection, the method comprising: monitoring operation of the DSL connection; detecting that the DSL connection is operating in a low power mode in which the signal power applied to the DSL connection by the DSL transceiver is at a first level below a power threshold value; increasing the signal power applied to the DSL connection to a second level above the power threshold value; recording data indicative of performance of the DSL connection with signal power applied to the DSL connection at the second level; and modifying DSL transceiver attributes based on the recorded data indicative of performance, to change operation of the DSL transceiver in transferring data over the DSL connection.

    Signal processing device and communication device
    10.
    发明授权
    Signal processing device and communication device 有权

    公开(公告)号：US09698816B2

    公开(公告)日：2017-07-04

    申请号：US15307044

    申请日：2015-01-28

    申请人： SUMITOMO ELECTRIC INDUSTRIES, LTD.

    发明人： Takashi Maehata

    IPC分类号： H03M3/00 ,  H03M3/02 ,  H04L27/00 ,  H04L1/00 ,  H04B1/7163

    CPC分类号： H03M3/30 ,  H03M3/02 ,  H03M3/402 ,  H04B1/71637 ,  H04L1/0003 ,  H04L27/00

    摘要： Reduction in signal intensity of a harmonic component included in an output of a delta-sigma modulator is suppressed. A signal processing device includes: a delta-sigma modulator 11 that outputs a pulse signal; a first processor 12 that generates, from the pulse signal PO outputted from the delta-sigma modulator 11, a discontinuous pulse signal PC in which each of one-pulse sections in the pulse signal PO has a low level region on at least one of a rear end and a front end of the one-pulse section; and a second processor that generates a short-width pulse signal PS having a pulse width shorter than a pulse width of the discontinuous pulse signal PC generated by the first processor 12.