Invention Grant
- Patent Title: Method of making biCMOS integrated circuit with shallow N-wells
- Patent Title (中): 使用浅N井制作biCMOS集成电路的方法
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Application No.: US783191Application Date: 1991-10-28
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Publication No.: US5198374APublication Date: 1993-03-30
- Inventor: Takao Kato
- Applicant: Takao Kato
- Applicant Address: JPX Tokyo
- Assignee: Oki Electric Industry Co., Ltd.
- Current Assignee: Oki Electric Industry Co., Ltd.
- Current Assignee Address: JPX Tokyo
- Priority: JPX2-87358 19900403
- Main IPC: H01L27/06
- IPC: H01L27/06
Abstract:
A biCMOS integrated circuit is created on a p-type semiconductor substrate on which first an n-type epitaxial layer then a p-type epitaxial layer is grown. NPN and PMOS transistors are formed in n-wells in the p-type epitaxial layer. n.sup.+ buried layers are located below the n-wells at the interface between the substrate and the n-type epitaxial layer. The n.sup.+ buried layers underlying the n-wells containing NPN transistors are surrounded by p.sup.+ buried layers that extend from the interface between the p-type and n-type epitaxial layers through the n-type epitaxial layers and into the substrate.
Public/Granted literature
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