发明授权
US5214770A System for flushing instruction-cache only when instruction-cache
address and data-cache address are matched and the execution of a
return-from-exception-or-interrupt command
失效
仅当指令高速缓存地址和数据高速缓存地址匹配并执行从异常或中断返回命令执行时，仅用于刷新指令缓存的系统
- 专利标题： System for flushing instruction-cache only when instruction-cache address and data-cache address are matched and the execution of a return-from-exception-or-interrupt command
- 专利标题（中）： 仅当指令高速缓存地址和数据高速缓存地址匹配并执行从异常或中断返回命令执行时，仅用于刷新指令缓存的系统
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申请号： US541485申请日： 1990-06-21
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公开(公告)号： US5214770A公开(公告)日： 1993-05-25
- 发明人: Raj K. Ramanujan , Peter J. Bannon , Simon C. Steely, Jr.
- 申请人： Raj K. Ramanujan , Peter J. Bannon , Simon C. Steely, Jr.
- 申请人地址： MA Maynard
- 专利权人： Digital Equipment Corporation
- 当前专利权人： Digital Equipment Corporation
- 当前专利权人地址： MA Maynard
- 主分类号： G06F9/38
- IPC分类号： G06F9/38
摘要：
A method and apparatus for optimizing the performance of a multiple cache system computer having separate caches for data and instructions in which all writes to the data cache are monitored. If the address tag of the item being written matches one of a list of tags representing valid instructions currently stored in the instruction cache, a flag called I.sub.-- FLUSH.sub.-- ON.sub.-- REI is set. Until this flag is set, REI (Return from Exception or Interrupt) instructions will not flush the instruction cache. When the flag is set, an REI command will also flush or clear the instruction cache. Thus, the instruction cache is only flushed when an address referenced by an instruction is modified, so as to reduce the number of times the cache is flushed and optimize the computer's speed of operation.
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