A process of manufacturing a trench-isolated semiconductor structure comprises forming a first `pad` (e.g. MOS gate) oxide layer on a first surface of a silicon substrate. An oxide etch protective layer of silicon nitride is selectively formed on a first portion of the pad oxide layer so as to overlie a first surface portion of the silicon substrate in which active device regions will be introduced. A second oxide layer is then deposited on the pad oxide layer and on the nitride layer. The dual oxide layer is then patterned to form a trench mask which exposes a second surface portion of the silicon substrate. An etchant is then applied to the structure so as to etch away material from the silicon substrate exposed by the second surface portion and a portion of the second oxide layer, thereby forming a trench in the second surface portion of the silicon substrate. After any remaining portion of the second oxide layer is removed, local oxidation of the structure is performed so as to form a third oxide layer in the trench and a field oxide at surface portions of the substrate adjacent to the nitride layer. A layer of polysilicon is non-selectively deposited over the entire structure to fill the oxide-lined trench and then polished down to the nitride layer which serves as a polishing stop. The nitride is then stripped off the pad oxide in preparation for device region processing.