发明授权
- 专利标题: High resolution, multi-frequency digital phase-locked loop
- 专利标题(中): 高分辨率,多频数字锁相环
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申请号: US890691申请日: 1992-05-29
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公开(公告)号: US5218314A公开(公告)日: 1993-06-08
- 发明人: Avner Efendovich , Afek Yachin , Amos Intrater , Zohar Peleg , Coby Sella , Zeev Bikowsky
- 申请人: Avner Efendovich , Afek Yachin , Amos Intrater , Zohar Peleg , Coby Sella , Zeev Bikowsky
- 申请人地址: CA Santa Clara
- 专利权人: National Semiconductor Corporation
- 当前专利权人: National Semiconductor Corporation
- 当前专利权人地址: CA Santa Clara
- 主分类号: H03L7/00
- IPC分类号: H03L7/00
摘要:
The present invention provides a phase-locked loop in which an internal oscillator is fed into a high resolution tapped delay line. One output of the tapped delay line is selected by selection logic to generate the output clock. The output clock is phase compared with the input signal, which is either a clock signal or a NRZ data signal, and in any case, is a signal with frequency that is a division by two of the frequency of the internal oscillator and the source of which is also the internal oscillator. Then a decision is made, according to the phase detection, whether to select the next output of the delay line, the previous one, or remain with the current one. Therefore, if a change in the frequency is needed, then if an integer multiple or division of the original frequency is selected for the internal oscillator, synchronization will be unchanged, and furthermore, both the output clock and the input signal will simultaneously switch to the new frequency. All this is done by additional logic that enables actual switching to the new frequency only after an entire cycle of the low frequency has ended.
公开/授权文献
- US5938670A Ablation devices and methods of use 公开/授权日:1999-08-17
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