An electrically-erasable, electrically-programmable read-only memory cell 10 is formed at a face of a layer of semiconductor 30 of a first conductivity type. A first source/drain region 16 and a second source/drain region 20 are formed in the face of layer of semiconductor 30 of a second conductivity type opposite the first conductivity type and spaced by a first channel area 50. A third source/drain region 18 is formed in the face of semiconductor layer 30 of the second conductivity type spaced from second source/drain region 20 by a second channel area 52. A thick insulator region 44 is formed adjacent at least a portion of second source/drain region 20 and includes a lateral margin of sloped thickness overlying a corresponding lateral margin of second source/drain region 20. The corresponding lateral margin of second source/drain region 20 has a graded dopant concentration directly proportionate with the sloped thickness of the overlying lateral margin of thick insulator region 44. A differentially grown insulator region 54 overlies second source/drain region 20 and includes a lateral margin of sloped thickness. A thin insulator tunneling window 62 overlies an area 60 of second source/drain region 20, tunneling window 62 formed between and spacing the lateral margin of the thick insulator region 44 and the lateral margin of differentially grown insulator region 54. A floating gate conductor 26 is disposed adjacent tunneling window 62 and insulatively adjacent second channel area 52. A control gate conductor 28 is disposed insulatively adjacent floating gate conductor 28. A gate conductor 24 is disposed insulatively adjacent first channel area 50.