公开(公告)号：US07630257B2

公开(公告)日：2009-12-08

申请号：US11543338

申请日：2006-10-04

Applicant: Sudhir Kumar Madan ,  Hugh P. Mcadams ,  Sung-Wei Lin

Inventor： Sudhir Kumar Madan ,  Hugh P. Mcadams ,  Sung-Wei Lin

IPC: G11C7/00

CPC classification number: G11C11/22 ,  G11C2207/005 ,  G11C2207/2281 ,  G11C2207/229

Abstract: One aspect of the invention relates to a method for accessing a memory device. One embodiment relates to a method for accessing a memory device. In the method during a read operation, one data value is provided on a local IO line while complimentary local IO line that is associated with the local IO line is inactivated. During a write operation, another data value is provided on the local IO line and a complimentary data value is provided on the complimentary local IO line. Other systems and methods are also disclosed.

Abstract translation: 本发明的一个方面涉及一种用于访问存储器件的方法。 一个实施例涉及访问存储器件的方法。 在读操作期间的方法中，在本地IO线上提供一个数据值，而与本地IO线相关联的互补本地IO线被停用。 在写操作期间，本地IO线上提供另一个数据值，并在互补的本地IO线上提供补充数据值。 还公开了其它系统和方法。

公开(公告)号：US20090010038A1

公开(公告)日：2009-01-08

申请号：US12234139

申请日：2008-09-19

Applicant: SUDHIR KUMAR MADAN ,  SUNG-WEI LIN ,  JOHN FONG

Inventor： SUDHIR KUMAR MADAN ,  SUNG-WEI LIN ,  JOHN FONG

IPC: G11C11/22

CPC classification number: G11C11/22 ,  H01L27/11502

Abstract: An FeRAM memory array wherein the plate lines run in the direction of word lines is described that provides a reduced plate line resistance in arrays having a common plate line connection. The lower plate line resistance reduces the magnitude of negative spikes on the plate line to reduce the potential for FeCap depolarization. Two or more plate lines of a plurality of columns of memory cells are interconnected along a bit line direction. Some or all of the plate lines of one or more columns of dummy memory cells may also be interconnected to reduce the plate line resistance and minimize any increase in the bit line capacitance for the active cells of the array. The improved FeRAM array provides a reduced data error rate, particularly at fast memory cycle times.

Abstract translation: 描述了其中板线在字线方向上延伸的FeRAM存储器阵列，其在具有公共板线连接的阵列中提供减小的板线电阻。 下板线电阻降低了板线上负尖峰的幅度，以减少FeCap去极化的可能性。 多列存储器单元的两条或多条板条沿位线方向互连。 一个或多个虚拟存储器单元列的一些或全部平板线也可互连，以减小板线电阻并且最小化阵列的有源单元的位线电容的任何增加。 改进的FeRAM阵列提供了降低的数据错误率，特别是在快速的存储周期时间。

公开(公告)号：US20070211510A1

公开(公告)日：2007-09-13

申请号：US11409628

申请日：2006-04-24

Applicant: Sudhir Madan ,  Sung-Wei Lin ,  John Fong

Inventor： Sudhir Madan ,  Sung-Wei Lin ,  John Fong

IPC: G11C11/22 ,  G11C5/06 ,  G11C11/42

CPC classification number: G11C11/22 ,  H01L27/11502

Abstract: An FeRAM memory array wherein the plate lines run in the direction of word lines is described that provides a reduced plate line resistance in arrays having a common plate line connection. The lower plate line resistance reduces the magnitude of negative spikes on the plate line to reduce the potential for FeCap depolarization. Two or more plate lines of a plurality of columns of memory cells are interconnected along a bit line direction. Some or all of the plate lines of one or more columns of dummy memory cells may also be interconnected to reduce the plate line resistance and minimize any increase in the bit line capacitance for the active cells of the array. The improved FeRAM array provides a reduced data error rate, particularly at fast memory cycle times.

Abstract translation: 描述了其中板线在字线方向上延伸的FeRAM存储器阵列，其在具有公共板线连接的阵列中提供减小的板线电阻。 下板线电阻降低了板线上负尖峰的幅度，以减少FeCap去极化的可能性。 多列存储器单元的两条或多条板条沿位线方向互连。 一个或多个虚拟存储器单元列的一些或全部平板线也可互连，以减小板线电阻并且最小化阵列的有源单元的位线电容的任何增加。 改进的FeRAM阵列提供了降低的数据错误率，特别是在快速的存储周期时间。

公开(公告)号：US20050207201A1

公开(公告)日：2005-09-22

申请号：US10805809

申请日：2004-03-22

Applicant: Sudhir Madan ,  Sung-Wei Lin ,  Hugh McAdams ,  Anand Seshadri ,  Jarrod Eliason

Inventor： Sudhir Madan ,  Sung-Wei Lin ,  Hugh McAdams ,  Anand Seshadri ,  Jarrod Eliason

IPC: G11C11/22 ,  G11C11/24

CPC classification number: G11C11/22

Abstract: Methods and ferroelectric devices are presented, in which pulses are selectively applied to ferroelectric memory cell wordlines to discharge cell storage node disturbances while the cell plateline and the associated bitline are held at substantially the same voltage.

Abstract translation: 提出了方法和铁电器件，其中脉冲被选择性地施加到铁电存储器单元字线以放电单元存储节点干扰，同时单元板线和相关联的位线保持在基本上相同的电压。

公开(公告)号：US5694073A

公开(公告)日：1997-12-02

申请号：US560768

申请日：1995-11-21

Applicant: Timothy J. Coots ,  Phat C. Truong ,  Sung-Wei Lin ,  Tim M. Coffman ,  Ming-Bo Liu ,  Ronald J. Syzdek

Inventor： Timothy J. Coots ,  Phat C. Truong ,  Sung-Wei Lin ,  Tim M. Coffman ,  Ming-Bo Liu ,  Ronald J. Syzdek

IPC: G01K7/00 ,  G01R19/00 ,  G05F3/24 ,  G05F3/26 ,  H03K17/14 ,  H03K17/16 ,  H03K17/687 ,  H03K19/003 ,  G05F3/02

CPC classification number: G05F3/262 ,  G05F3/247 ,  H03K19/00384

Abstract: A supply-voltage detecting stage (11) that supplies first and second reference currents (I.sub.REFP and I.sub.REFN) which vary with the supply voltage (V.sub.cc) and are coupled by first and second gain stages (12A and 12B), respectively, to first and second temperature-detecting stages (13A and 13B), respectively. First and second temperature-detecting stages (13A and 13B) increase the coupled reference currents (I.sub.REFP and I.sub.REFN), respectively, to compensate for temperature increase through use temperature-sensitive, long-channel transistors (M34-M37 and M42-M45), supplying temperature and supply-voltage compensated output bias voltages at output terminals (MIRN and MIRP).

Abstract translation: 电源电压检测级（11），其提供第一和第二参考电流（IREFP和IREFN），其随着电源电压（Vcc）而变化并分别由第一和第二增益级（12A和12B）耦合到第一和第二增益级 第二温度检测级（13A和13B）。 第一和第二温度检测级（13A和13B）分别增加耦合的参考电流（IREFP和IREFN），以通过使用温度敏感的长沟道晶体管（M34-M37和M42-M45）补偿温度升高， 在输出端子（MIRN和MIRP）提供温度和电源电压补偿输出偏置电压。

公开(公告)号：US5491809A

公开(公告)日：1996-02-13

申请号：US764

申请日：1993-01-05

Applicant: Tim M. Coffman ,  Sung-Wei Lin ,  T. Damodar Reddy

Inventor： Tim M. Coffman ,  Sung-Wei Lin ,  T. Damodar Reddy

IPC: G11C17/00 ,  G11C16/02 ,  G11C16/22 ,  G11C16/34 ,  G06F12/16

CPC classification number: G11C16/3445 ,  G11C16/22 ,  G11C16/344

Abstract: A method for erasing blocks of a non-volatile memory includes detecting whether a block is in at least one of an erased state or a state secured from erasure; then setting a flag register at a first level for each block detected to be in at least one of an erased state or a state secured from erasure or at a second level for each block not so detected; then selecting for erasure blocks that have their respective flags set at the second level; and then erasing the selected blocks.

Abstract translation: 一种用于擦除非易失性存储器的块的方法，包括：检测块是否处于擦除状态或从擦除中保护的状态中的至少一个; 然后将每个被检测到的块中的每个块设置为处于擦除状态或从擦除保护的状态中的至少一个或者对于不被检测到的每个块的第二级的标志寄存器; 然后选择其各自的标志设置在第二级的擦除块; 然后擦除所选的块。

公开(公告)号：US5450417A

公开(公告)日：1995-09-12

申请号：US149243

申请日：1993-10-26

Applicant: Phat C. Truong ,  Tim M. Coffman ,  Sung-Wei Lin ,  T. Damodar Reddy ,  Dennis R. Robinson

Inventor： Phat C. Truong ,  Tim M. Coffman ,  Sung-Wei Lin ,  T. Damodar Reddy ,  Dennis R. Robinson

IPC: H03K3/356 ,  H03K17/22 ,  H04B17/00

CPC classification number: H03K3/356008 ,  H03K17/22

Abstract: The power-on-reset test circuit of this invention includes two imbalanced latches to detect the occurrence of a transient power-on-reset signal. The occurrence of a transient power-on-reset signal is latched for later verification during circuit testing. Both latches are designed to default to a low voltage output (Vss) on initial power-up. One of the latches is set by the power-on-reset signal to a high-voltage output (Vcc) state. The other latch is set by a reference-potential input to a low-voltage output state. If the set latch has a high-voltage output and the other latch has a low-voltage output, then the power-on-reset circuitry is functioning properly.

Abstract translation: 本发明的上电复位测试电路包括两个不平衡锁存器，用于检测瞬态上电复位信号的发生。 瞬态上电复位信号的发生被锁存用于电路测试期间的后续验证。 两个锁存器都设计为在初始上电时默认为低电压输出（Vss）。 其中一个锁存器由上电复位信号设置为高电压输出（Vcc）状态。 另一个锁存器由参考电位输入设置为低电压输出状态。 如果设置的锁存器具有高电压输出，另一个锁存器具有低电压输出，则上电复位电路正常工作。

公开(公告)号：US5397946A

公开(公告)日：1995-03-14

申请号：US149246

申请日：1993-10-26

Applicant: Phat C. Truong ,  Tim M. Coffman ,  Sung-Wei Lin ,  T. Damodar Reddy ,  Dennis R. Robinson

Inventor： Phat C. Truong ,  Tim M. Coffman ,  Sung-Wei Lin ,  T. Damodar Reddy ,  Dennis R. Robinson

IPC: G11C17/00 ,  G11C5/14 ,  G11C16/06 ,  G11C16/22 ,  G11C29/00 ,  G11C29/12 ,  H03F3/193 ,  G11C7/00

CPC classification number: G11C5/143 ,  G11C16/225

Abstract: The CMOS high-voltage sensor circuit has a voltage reference including, for example, of four N-channel MOS transistors; one pass-gate P-channel transistor; one current-mirror P-channel MOS transistor; and a conventional high-voltage sensor including, for example, of two P-channel MOS transistors and one N-channel MOS transistor. The sensor circuit of this invention generates a high-voltage signal at the output if the input voltage is greater than both the reference voltage plus two P-channel threshold voltages and the supply voltage Vcc plus two P-channel threshold voltages. The power-up or power-down sequence may be in any order without adversely affecting the operation of the circuit of this invention.

Abstract translation: CMOS高电压传感器电路具有包括例如四个N沟道MOS晶体管的电压基准; 一个通道P沟道晶体管; 一个电流镜P沟道MOS晶体管; 以及包括例如两个P沟道MOS晶体管和一个N沟道MOS晶体管的常规高压传感器。 如果输入电压大于参考电压加上两个P沟道阈值电压和电源电压Vcc加上两个P沟道阈值电压，本发明的传感器电路在输出端产生高电压信号。 上电或断电顺序可以是任何顺序，而不会不利地影响本发明的电路的操作。

公开(公告)号：US5218568A

公开(公告)日：1993-06-08

申请号：US809462

申请日：1991-12-17

Applicant: Sung-Wei Lin ,  Manzur Gill ,  Inn K. Lee

Inventor： Sung-Wei Lin ,  Manzur Gill ,  Inn K. Lee

IPC: G11C16/04 ,  H01L21/8247 ,  H01L27/115

CPC classification number: H01L27/11521 ,  G11C16/0433 ,  H01L27/115 ,  H01L27/11524

Abstract: An electrically-erasable, electrically-programmable read-only memory cell 10 is formed at a face of a layer of semiconductor 30 of a first conductivity type. A first source/drain region 16 and a second source/drain region 20 are formed in the face of layer of semiconductor 30 of a second conductivity type opposite the first conductivity type and spaced by a first channel area 50. A third source/drain region 18 is formed in the face of semiconductor layer 30 of the second conductivity type spaced from second source/drain region 20 by a second channel area 52. A thick insulator region 44 is formed adjacent at least a portion of second source/drain region 20 and includes a lateral margin of sloped thickness overlying a corresponding lateral margin of second source/drain region 20. The corresponding lateral margin of second source/drain region 20 has a graded dopant concentration directly proportionate with the sloped thickness of the overlying lateral margin of thick insulator region 44. A differentially grown insulator region 54 overlies second source/drain region 20 and includes a lateral margin of sloped thickness. A thin insulator tunneling window 62 overlies an area 60 of second source/drain region 20, tunneling window 62 formed between and spacing the lateral margin of the thick insulator region 44 and the lateral margin of differentially grown insulator region 54. A floating gate conductor 26 is disposed adjacent tunneling window 62 and insulatively adjacent second channel area 52. A control gate conductor 28 is disposed insulatively adjacent floating gate conductor 28. A gate conductor 24 is disposed insulatively adjacent first channel area 50.

Abstract translation: 电可擦除的电可编程只读存储单元10形成在第一导电类型的半导体层30的表面。 第一源极/漏极区域16和第二源极/漏极区域20形成在与第一导电类型相反并且由第一沟道区域50间隔开的第二导电类型的半导体层30的表面中。第三源极/漏极区域 18形成在第二导电类型的半导体层30的表面上，第二导电类型的第二导电类型与第二源极/漏极区域20间隔开第二沟道区域52.邻近第二源极/漏极区域20的至少一部分形成厚的绝缘体区域44， 包括覆盖第二源极/漏极区域20的相应横向边缘的倾斜厚度的横向边缘。第二源极/漏极区域20的对应横向边缘具有与厚度绝缘体的上覆侧边缘的倾斜厚度成正比的渐变掺杂剂浓度 差分生长的绝缘体区域54覆盖第二源极/漏极区域20并且包括倾斜厚度的侧向边缘。 薄的绝缘体隧道窗口62覆盖在第二源极/漏极区域20的区域60之间，形成在厚绝缘体区域44的侧边缘之间并且间隔着厚的绝缘体区域44的侧边缘和差分生长的绝缘体区域54的横向边缘之间的隧道窗口62.浮动栅极导体26 被布置在相邻的隧道窗口62和绝对相邻的第二通道区域52处。控制栅极导体28被隔离地邻近浮置栅极导体28设置。栅极导体24与第一沟道区域50绝缘地邻近设置。

公开(公告)号：US5155055A

公开(公告)日：1992-10-13

申请号：US685358

申请日：1991-04-15

Applicant: Manzur Gill ,  Sung-Wei Lin ,  C. Rinn Cleavelin ,  David J. McElroy

Inventor： Manzur Gill ,  Sung-Wei Lin ,  C. Rinn Cleavelin ,  David J. McElroy

IPC: H01L21/8247 ,  H01L29/788

CPC classification number: H01L27/11517 ,  H01L29/7883

Abstract: An electrically-erasable, electrically-programmable ROM or an EEPROM is constructed using an enhancement transistor merged with a floating-gate transistor, where the floating-gate transistor has a small self-aligned tunnel window positioned on the opposite side of the source from the channel and drain, in a contact-free cell layout, enhancing the ease of manufacture and reducing cell size. In this cell, the bitlines and source/drain regions are buried beneath relatively thick silicon oxide, which allows a favorable ratio of control gate to floating gate capacitance. Programming and erasing are provided by the tunnel window area on the outside of the source (spaced from the channel). The tunnel window has a thinner dielectric than the remainder of the floating gate to allow Fowler-Nordheim tunneling.

Abstract translation: 使用与浮栅晶体管合并的增强型晶体管构造电可擦除的电可编程ROM或EEPROM，其中浮栅晶体管具有位于源极的相对侧上的小的自对准隧道窗口 通道和漏极，无接触电池布局，增强了制造的便利性和减小电池尺寸。 在该单元中，位线和源极/漏极区域被埋在相对较厚的氧化硅之下，这允许控制栅极与浮动栅极电容的有利比例。 编程和擦除由源外部的隧道窗口区域（与通道间隔开）提供。 隧道窗口具有比浮动门的其余部分更薄的电介质，以允许Fowler-Nordheim隧道。