A signal processor which is specially adapted for decoding sequential codes, including trellis codes, convolutional codes and detecting signals in partial response channels. The processor has three units, a branch metric generator unit, an add-compare-select unit and a survivor-trace and decoding unit, each of which is independently programmable. A central control unit synchronizes operations between the units at the received symbol rate. Between synchronizations, each of the units operate concurrently and independently of the others.