A self-aligned, under-gated TFT device (10). A base layer (14) is formed. A conductive layer (16) is formed overlying the base layer (14). A dielectric layer (18) is formed overlying the conductive layer (16). A sacrificial layer (20) is formed overlying the dielectric layer (18). The layers (16, 18, and 20) are etched to form a "pillar" region. A dielectric layer (22) and a planar layer (24), which both overlie the "pillar" region, are etched back to form a substantially planar surface and expose a top portion of the sacrificial layer (20). The sacrificial layer (20) is removed and a conductive layer (28) is formed overlying conductive region (16) and planar layer (22). Conductive layer (28) is used to form a self-aligned TFT device (10) via the formation of a source region (33) and a drain region (34) adjacent an aligned plug region (32).