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1.发明授权
公开(公告)号：US5235189A
公开(公告)日：1993-08-10
申请号：US923649
申请日：1992-08-03
申请人： James D. Hayden , Bich-Yen Nguyen , Cooper Kent J.
发明人： James D. Hayden , Bich-Yen Nguyen , Cooper Kent J.
IPC分类号： H01L21/336 , H01L21/84 , H01L29/786
CPC分类号： H01L29/66765 , H01L21/84 , H01L29/78678
摘要： A self-aligned, under-gated TFT device (10). A base layer (14) is formed. A conductive layer (16) is formed overlying the base layer (14). A dielectric layer (18) is formed overlying the conductive layer (16). A sacrificial layer (20) is formed overlying the dielectric layer (18). The layers (16, 18, and 20) are etched to form a "pillar" region. A dielectric layer (22) and a planar layer (24), which both overlie the "pillar" region, are etched back to form a substantially planar surface and expose a top portion of the sacrificial layer (20). The sacrificial layer (20) is removed and a conductive layer (28) is formed overlying conductive region (16) and planar layer (22). Conductive layer (28) is used to form a self-aligned TFT device (10) via the formation of a source region (33) and a drain region (34) adjacent an aligned plug region (32).
摘要翻译： 一种自对准的下栅极TFT器件（10）。 形成基层（14）。 形成在基底层（14）上方的导电层（16）。 形成在导电层（16）上方的电介质层（18）。 形成覆盖在电介质层（18）上的牺牲层（20）。 层（16,18和20）被蚀刻以形成“柱”区域。 将覆盖在“柱”区域上的电介质层（22）和平面层（24）被回蚀刻以形成基本上平坦的表面并且暴露牺牲层（20）的顶部部分。 去除牺牲层（20），并且形成覆盖导电区域（16）和平面层（22）的导电层（28）。 导电层（28）用于通过形成邻近对准的插塞区域（32）的源区（33）和漏区（34）来形成自对准TFT器件（10）。
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公开(公告)号：US5567958A
公开(公告)日：1996-10-22
申请号：US452944
申请日：1995-05-31
IPC分类号： H01L21/336 , H01L27/11 , H01L29/786 , H01L29/78
CPC分类号： H01L27/1108 , H01L29/66757 , H01L29/78696 , Y10S257/903
摘要： A thin-film transistor and SRAM memory cell include thin-film source and drain regions (12, 14) separated by an opening (22) and overlying and insulating layer (11). A thin-film channel layer (16) overlies the thin-film source and drain regions (12, 14) and a portion of the insulating layer (11) exposed by the opening (22). A thin-film gate electrode (20) is positioned in the opening (22) and defines a thin-film channel region (24) in the thin-film channel layer (16). The thin-film gate electrode (20) is separated from the thin-film channel region (24) by a gate dielectric layer (18). The thin-film channel region (24) extends along vertical wall surfaces (26, 28) of the thin-film source and drain regions (12, 14) providing an extended channel length for the thin-film transistor.
摘要翻译： 薄膜晶体管和SRAM存储单元包括由开口（22）和上覆绝缘层（11）分开的薄膜源区和漏区（12,14）。 薄膜通道层（16）覆盖薄膜源区和漏区（12,14），绝缘层（11）的一部分由开口（22）露出。 薄膜栅电极（20）位于开口（22）中并且在薄膜通道层（16）中限定薄膜通道区（24）。 薄膜栅电极（20）通过栅介质层（18）与薄膜沟道区（24）分离。 薄膜通道区域（24）沿薄膜源极和漏极区域（12,14）的垂直壁表面（26,28）延伸，为薄膜晶体管提供延长的沟道长度。
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公开(公告)号：US5543635A
公开(公告)日：1996-08-06
申请号：US455268
申请日：1995-05-31
IPC分类号： H01L21/336 , H01L21/8244 , H01L27/11 , H01L29/786 , H01L29/76 , H01L29/04 , H01L31/036 , H01L31/112
CPC分类号： H01L29/66765 , H01L27/11 , H01L27/1108 , H01L29/78618 , H01L29/78624 , H01L29/78678 , Y10S148/109
摘要： An under-gated thin film transistor (54) having low leakage current and a high on/off current ratio is formed using a composite layer (40) of semiconducting material. In one embodiment a composite layer (40) of semiconducting layer is formed by depositing two distinct layers (34, 38) of semiconducting material over the transistor gate electrode (18). The composite layer (40) is then patterned and implanted with ions to form a source region (46) and a drain region (48) within the composite layer (40), and to define a channel region (50) and an offset drain region (52) within the composite layer (40).
摘要翻译： 使用半导体材料的复合层（40）形成具有低漏电流和高导通/截止电流比的欠门控薄膜晶体管（54）。 在一个实施例中，通过在晶体管栅电极（18）上沉积半导体材料的两个不同的层（34,38）形成半导体层的复合层（40）。 然后将复合层（40）图案化并注入离子，以在复合层（40）内形成源区（46）和漏区（48），并且限定沟道区（50）和偏移漏区 （52）内。
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公开(公告)号：US5158898A
公开(公告)日：1992-10-27
申请号：US794279
申请日：1991-11-19
申请人： James D. Hayden , Bich-Yen Nguyen , Kent J. Cooper
发明人： James D. Hayden , Bich-Yen Nguyen , Kent J. Cooper
IPC分类号： H01L29/78 , H01L21/336 , H01L21/84 , H01L29/786
CPC分类号： H01L29/66765 , H01L21/84 , H01L29/78678
摘要： A self-aligned, under-gated TFT device (10). A base layer (14) is formed. A conductive layer (16) is formed overlying the base layer (14). A dielectric layer (18) is formed overlying the conductive layer (16). A sacrificial layer (20) is formed overlying the dielectric layer (18). The layers (16, 18, and 20) are etched to form a "pillar" region. A dielectric layer (22) and a planar layer (24), which both overlie the "pillar" region, are etched back to form a substantially planar surface and expose a top portion of the sacrificial layer (20). The sacrificial layer (20) is removed and a conductive layer (28) is formed overlying conductive region (16) and planar layer (22). Conductive layer (28) is used to form a self-aligned TFT device (10) via the formation of a source region (33) and a drain region (34) adjacent an aligned plug region (32).
摘要翻译： 一种自对准的下栅极TFT器件（10）。 形成基层（14）。 形成在基底层（14）上方的导电层（16）。 形成在导电层（16）上方的电介质层（18）。 形成覆盖在电介质层（18）上的牺牲层（20）。 层（16,18和20）被蚀刻以形成“柱”区域。 将覆盖在“柱”区域上的电介质层（22）和平面层（24）被回蚀刻以形成基本上平坦的表面并且暴露牺牲层（20）的顶部部分。 去除牺牲层（20），并且形成覆盖导电区域（16）和平面层（22）的导电层（28）。 导电层（28）用于通过形成邻近对准的插塞区域（32）的源区（33）和漏区（34）来形成自对准TFT器件（10）。
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公开(公告)号：US5262352A
公开(公告)日：1993-11-16
申请号：US937025
申请日：1992-08-31
IPC分类号： H01L21/60 , H01L21/768 , H01L23/485 , H01L21/44 , H01L21/48
CPC分类号： H01L21/76831 , H01L21/76805 , H01L21/76834 , H01L21/76897 , H01L23/485 , H01L23/5226 , H01L2924/0002
摘要： An interconnect structure is formed having a substrate (10). A conductive layer (14) is formed overlying the substrate (10). A conductive layer (18) is formed overlying the conductive layer (14). An opening (19) is etched through the conductive layer (18), exposing a top portion of conductive layer (14), and forming a sidewall of the conductive layer (18). An selective isotropic etch procedure is used to laterally recess the sidewall of the conductive layer (18). A sidewall spacer (22) is formed adjacent the sidewall of the conductive layer (18). A conductive layer (24) is formed within opening (19) and adjacent the spacer (22) to form an interconnection between conductive layers (24 and 14). The interconnection is self-aligned, and conductive layer (18) is reliably isolated from the interconnect due to the lateral recessed sidewall of the conductive layer (18).
摘要翻译： 形成具有衬底（10）的互连结构。 形成在衬底（10）上方的导电层（14）。 形成覆盖导电层（14）的导电层（18）。 通过导电层（18）蚀刻开口（19），暴露导电层（14）的顶部部分，并形成导电层（18）的侧壁。 使用选择性各向同性蚀刻工艺来横向凹入导电层（18）的侧壁。 邻近导电层（18）的侧壁形成侧壁间隔物（22）。 导电层（24）形成在开口（19）内并与隔离物（22）相邻以形成导电层（24和14）之间的互连。 互连是自对准的，并且由于导电层（18）的侧向凹入的侧壁，导电层（18）可靠地与互连隔离。
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公开(公告)号：US5408130A
公开(公告)日：1995-04-18
申请号：US286592
申请日：1994-08-05
IPC分类号： H01L21/60 , H01L21/768 , H01L23/485 , H01L23/48 , H01L29/46 , H01L29/62
CPC分类号： H01L21/76831 , H01L21/76805 , H01L21/76834 , H01L21/76897 , H01L23/485 , H01L23/5226 , H01L2924/0002
摘要： An interconnect structure is formed having a substrate (10). A conductive layer (14) is formed overlying the substrate (10). A conductive layer (18) is formed overlying the conductive layer (14). An opening (19) is etched through the conductive layer (18), exposing a top portion of conductive layer (14), and forming a sidewall of the conductive layer (18). An selective isotropic etch procedure is used to laterally recess the sidewall of the conductive layer (18). A sidewall spacer (22) is formed adjacent the sidewall of the conductive layer (18). A conductive layer (24) is formed within opening (19) and adjacent the spacer (22) to form an interconnection between conductive layers (24 and 14). The interconnection is self-aligned, and conductive layer (18) is reliably isolated from the interconnect due to the lateral recessed sidewall of the conductive layer (18).
摘要翻译： 形成具有衬底（10）的互连结构。 形成在衬底（10）上方的导电层（14）。 形成覆盖导电层（14）的导电层（18）。 通过导电层（18）蚀刻开口（19），暴露导电层（14）的顶部部分，并形成导电层（18）的侧壁。 使用选择性各向同性蚀刻工艺来横向凹入导电层（18）的侧壁。 邻近导电层（18）的侧壁形成侧壁间隔物（22）。 导电层（24）形成在开口（19）内并与隔离物（22）相邻以形成导电层（24和14）之间的互连。 互连是自对准的，并且由于导电层（18）的侧向凹入的侧壁，导电层（18）可靠地与互连隔离。
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公开(公告)号：US5510278A
公开(公告)日：1996-04-23
申请号：US300770
申请日：1994-09-06
IPC分类号： H01L21/336 , H01L21/8244 , H01L27/11 , H01L29/786 , H01L21/786
CPC分类号： H01L29/66765 , H01L27/11 , H01L27/1108 , H01L29/78618 , H01L29/78624 , H01L29/78678 , Y10S148/109
摘要： An under-gated thin film transistor (54) having low leakage current and a high on/off current ratio is formed using a composite layer (40) of semiconducting material. In one embodiment a composite layer (40) of semiconducting layer is formed by depositing two distinct layers (34, 38) of semiconducting material over the transistor gate electrode (18). The composite layer (40) is then patterned and implanted with ions to form a source region (46) and a drain region (48) within the composite layer (40), and to define a channel region (50) and an offset drain region (52) within the composite layer (40).
摘要翻译： 使用半导体材料的复合层（40）形成具有低漏电流和高导通/截止电流比的欠门控薄膜晶体管（54）。 在一个实施例中，通过在晶体管栅电极（18）上沉积半导体材料的两个不同的层（34,38）形成半导体层的复合层（40）。 然后将复合层（40）图案化并注入离子，以在复合层（40）内形成源区（46）和漏区（48），并且限定沟道区（50）和偏移漏区 （52）内。
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8.发明授权公开(公告)号：US08842945B2
公开(公告)日：2014-09-23
申请号：US13206299
申请日：2011-08-09
申请人： Bich-Yen Nguyen , Mariam Sadaka
发明人： Bich-Yen Nguyen , Mariam Sadaka
IPC分类号： G02B6/12 , H01L25/16 , H01L27/06 , H01L31/103
CPC分类号： H01L25/167 , G02B6/12002 , G02B6/12004 , H01L27/0688 , H01L27/1203 , H01L31/103 , H01L33/34 , H01L2924/0002 , H01L2924/00
摘要： Three dimensionally integrated semiconductor systems include a photoactive device operationally coupled with a current/voltage converter on a semiconductor-on-insulator (SeOI) substrate. An optical interconnect is operatively coupled to the photoactive device. A semiconductor device is bonded over the SeOI substrate, and an electrical pathway extends between the current/voltage converter and the semiconductor device bonded over the SeOI substrate. Methods of forming such systems include forming a photoactive device on an SeOI substrate, and operatively coupling a waveguide with the photoactive device. A current/voltage converter may be formed over the SeOI substrate, and the photoactive device and the current/voltage converter may be operatively coupled with one another. A semiconductor device may be bonded over the SeOI substrate and operatively coupled with the current/voltage converter.
摘要翻译： 三维集成的半导体系统包括在绝缘体上半导体（SeOI）衬底上与电流/电压转换器可操作地耦合的光活性器件。 光学互连可操作地耦合到光活性器件。 半导体器件接合在SeOI衬底上，并且电路在电流/电压转换器和接合在SeOI衬底上的半导体器件之间延伸。 形成这种系统的方法包括在SeOI衬底上形成光活性器件，并且可操作地将波导与光活性器件耦合。 可以在SeOI衬底上形成电流/电压转换器，并且光敏器件和电流/电压转换器可以彼此可操作地耦合。 半导体器件可以接合在SeOI衬底上并且与电流/电压转换器可操作地耦合。
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公开(公告)号：US08654602B2
公开(公告)日：2014-02-18
申请号：US13495632
申请日：2012-06-13
申请人： Carlos Mazure , Richard Ferrant , Bich-Yen Nguyen
发明人： Carlos Mazure , Richard Ferrant , Bich-Yen Nguyen
IPC分类号： G11C8/00
CPC分类号： G11C8/08 , G11C11/4085 , G11C2211/4016
摘要： A circuit made on a semiconductor-on-insulator substrate. The circuit includes a first transistor having a first channel, a second transistor having a second channel, with the transistors provided in serial association between first and second terminals for applying a power supply potential, each of the transistors comprising a drain region and a source region in the thin layer, a channel extending between the source region and the drain region, and a front control gate located above the channel. Each transistor has a back control gate formed in the base substrate below the channel of the transistor and capable of being biased in order to modulate the threshold voltage of the transistor. At least one of the transistors is configured for operating in a depletion mode under the action of a back gate signal which will sufficiently modulate its threshold voltage.
摘要翻译： 在绝缘体上半导体衬底上制成的电路。 该电路包括具有第一通道的第一晶体管，具有第二通道的第二晶体管，晶体管以第一和第二端子串联连接的方式提供，以施加电源电位，每个晶体管包括漏极区域和源极区域 在薄层中，在源极区域和漏极区域之间延伸的沟道以及位于沟道上方的前部控制栅极。 每个晶体管具有形成在晶体管的沟道下方的基底衬底中的背控制栅极，并且能够被偏置以便调制晶体管的阈值电压。 晶体管中的至少一个被配置为在充分调制其阈值电压的背栅信号的作用下以耗尽模式工作。
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公开(公告)号：US20110242926A1
公开(公告)日：2011-10-06
申请号：US12793553
申请日：2010-06-03
申请人： Carlos Mazure , Richard Ferrant , Bich-Yen Nguyen
发明人： Carlos Mazure , Richard Ferrant , Bich-Yen Nguyen
CPC分类号： G11C8/08 , G11C11/4085 , G11C2211/4016
摘要： A circuit made on a semiconductor-on-insulator substrate. The circuit includes a first transistor having a first channel, a second transistor having a second channel, with the transistors provided in serial association between first and second terminals for applying a power supply potential, each of the transistors comprising a drain region and a source region in the thin layer, a channel extending between the source region and the drain region, and a front control gate located above the channel. Each transistor has a back control gate formed in the base substrate below the channel of the transistor and capable of being biased in order to modulate the threshold voltage of the transistor. At least one of the transistors is configured for operating in a depletion mode under the action of a back gate signal which will sufficiently modulate its threshold voltage.
摘要翻译： 在绝缘体上半导体衬底上制成的电路。 该电路包括具有第一通道的第一晶体管，具有第二通道的第二晶体管，晶体管以第一和第二端子串联连接的方式提供，以施加电源电位，每个晶体管包括漏极区域和源极区域 在薄层中，在源极区域和漏极区域之间延伸的沟道以及位于沟道上方的前部控制栅极。 每个晶体管具有形成在晶体管的沟道下方的基底衬底中的背控制栅极，并且能够被偏置以便调制晶体管的阈值电压。 晶体管中的至少一个被配置为在充分调制其阈值电压的背栅信号的作用下以耗尽模式工作。
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