发明授权
US5235688A Memory access control unit for allowing maximum throughput of an I/O
processor and an I/O request buffer full state
失效
用于允许I / O处理器和I / O请求缓冲器的最大吞吐量的存储器访问控制单元
- 专利标题： Memory access control unit for allowing maximum throughput of an I/O processor and an I/O request buffer full state
- 专利标题（中）： 用于允许I / O处理器和I / O请求缓冲器的最大吞吐量的存储器访问控制单元
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申请号： US532446申请日： 1990-06-04
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公开(公告)号： US5235688A公开(公告)日： 1993-08-10
- 发明人: Toshihisa Taniguchi , Tsutomu Sumimoto
- 申请人： Toshihisa Taniguchi , Tsutomu Sumimoto
- 申请人地址： JPX Tokyo
- 专利权人： Hitachi, Ltd.
- 当前专利权人： Hitachi, Ltd.
- 当前专利权人地址： JPX Tokyo
- 优先权： JPX1-156169 19890619
- 主分类号： G06F9/50
- IPC分类号： G06F9/50 ; G06F9/52 ; G06F12/00 ; G06F12/08 ; G06F15/16 ; G06F15/177
摘要：
When an IOP is transferring data at the maximal throughput because of the fact that the input-output processor (IOP) has issued a next request under a state when the request buffers are full of requests from the IOP at least a part of the requests from the instruction processor (IP) is inhibited. Inhibition of the requests from the IP is released when the pitch of the requests from the IOP reaches a predetermined period or more. When the IOP is transferring data at the maximal throughput in a system having a cache memory, access to the main memory by the IP is inhibited in case requested data does not exist in the cache memory.
公开/授权文献
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