发明授权
US5239212A Gate circuit of combined field-effect and bipolar transistors with an
improved discharge arrangement
失效
具有改善放电布置的组合场效应和双极晶体管的栅极电路
- 专利标题： Gate circuit of combined field-effect and bipolar transistors with an improved discharge arrangement
- 专利标题（中）： 具有改善放电布置的组合场效应和双极晶体管的栅极电路
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申请号： US986891申请日： 1992-12-08
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公开(公告)号： US5239212A公开(公告)日： 1993-08-24
- 发明人: Ikuro Masuda , Kazuo Kato , Takao Sasayama , Yoji Nishio , Shigeo Kuboki , Masahiro Iwamura
- 申请人： Ikuro Masuda , Kazuo Kato , Takao Sasayama , Yoji Nishio , Shigeo Kuboki , Masahiro Iwamura
- 申请人地址： JPX Tokyo
- 专利权人： Hitachi, Ltd.
- 当前专利权人： Hitachi, Ltd.
- 当前专利权人地址： JPX Tokyo
- 优先权： JPX57-119815 19820712
- 主分类号： H01L27/06
- IPC分类号： H01L27/06 ; H03K19/01 ; H03K19/017 ; H03K19/0944
摘要：
A high-speed operation, low-power consumption gate circuit structure comprises a combination of complementary field-effect-transistors and bipolar transistors and discharge means for discharging accumulated charges from these transistors when the field-effect-transistors and bipolar transistors are turned off.
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