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    EXCESSIVE CURRENT PROTECTION FOR BOOTSTRAP CAPACITOR CHARGING
    1.
    发明公开
    EXCESSIVE CURRENT PROTECTION FOR BOOTSTRAP CAPACITOR CHARGING 审中-公开

    公开(公告)号：US20240364337A1

    公开(公告)日：2024-10-31

    申请号：US18308100

    申请日：2023-04-27

    申请人： TEXAS INSTRUMENTS INCORPORATED

    发明人： Weibing Jing ,  Dan Li

    IPC分类号： H03K19/017 ,  H03K17/06 ,  H03K17/081

    CPC分类号： H03K19/01714 ,  H03K17/063 ,  H03K17/08104

    摘要： According to some aspects, a circuit, such as an integrated circuit, comprises a bootstrap capacitor terminal, a bootstrap capacitor charging circuit coupled to the bootstrap capacitor terminal; and a bootstrap capacitor charging current limiting circuit coupled to the bootstrap capacitor charging circuit. According to some aspects, the circuit comprises a capacitor terminal, a capacitor charging transistor coupled to the capacitor terminal, a capacitor charging current sensing transistor coupled to the capacitor charging transistor, a current programming transistor coupled to the capacitor charging current sensing transistor; and a capacitor current limiting transistor coupled to the capacitor charging current sensing transistor, to the current programming transistor, and to the capacitor charging transistor. According to some aspects, an apparatus comprises a memory storing instructions to cause a processor to instantiate bootstrap capacitor charging current limiting circuit features.

    SEMICONDUCTOR DEVICE
    2.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240355833A1

    公开(公告)日：2024-10-24

    申请号：US18599439

    申请日：2024-03-08

    申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

    发明人： Takahiko ISHIZU ,  Seiichi YONEDA

    IPC分类号： H01L27/12 ,  H01L29/24 ,  H03K19/003 ,  H03K19/017 ,  H03K19/094 ,  H03K19/20

    CPC分类号： H01L27/124 ,  H01L27/1259 ,  H01L29/24 ,  H03K19/00315 ,  H03K19/017 ,  H03K19/0941 ,  H03K19/20

    摘要： A semiconductor device capable of stable operation with low power consumption is provided. A logic circuit having a circuit configuration using a transistor including an oxide semiconductor in a channel formation region is included. The logic circuit is a two-input/two-output two-wire logic circuit. Transistors included in the logic circuit each include a gate and a back gate. An input terminal is electrically connected to one of a gate and a back gate of a transistor electrically connected to a wiring for supplying a high power supply potential. An output terminal is connected to the other of the gate and the back gate of the transistor electrically connected to the wiring for supplying a high power supply potential. An output terminal is electrically connected to one of a source and a drain of a transistor electrically connected to a wiring for supplying a low power supply potential. A gate or a back gate of the transistor electrically connected to the wiring for supplying a low power supply potential is electrically connected to an input terminal.

    ZQ CALIBRATION CIRCUIT, OPERATION METHOD, MEMORY AND MEMORY SYSTEM
    3.
    发明公开
    ZQ CALIBRATION CIRCUIT, OPERATION METHOD, MEMORY AND MEMORY SYSTEM 审中-公开

    公开(公告)号：US20240331743A1

    公开(公告)日：2024-10-03

    申请号：US18227264

    申请日：2023-07-27

    申请人： YANGTZE MEMORY TECHNOLOGIES CO., LTD.

    发明人： Huiyuan Yue ,  Shiyang Yang

    IPC分类号： G11C7/10 ,  H03K19/017

    CPC分类号： G11C7/1063 ,  G11C7/1012 ,  G11C7/106 ,  H03K19/01721 ,  G11C2207/2254

    摘要： Implementations of the present disclosure disclose a circuit for ZQ calibration. The circuit may include a logic control circuit. The logic control circuit may include a calibration code generation circuit configured to generate an initial calibration code in response to a calibration command. The logic control circuit may include a mapping conversion circuit configured to control the calibration code generation circuit to convert the initial calibration code to a target calibration code of a target adjustment step size in response to a code adjustment signal. The circuit may further include a calibration circuit configured to calibrate interface impedance of a target semiconductor device based on the target calibration code.

    COMPACT AND HIGH-SPEED OCTAL CLOCK PHASE GENERATOR FOR PHASE INTERPOLATOR APPLICATIONS
    4.
    发明公开
    COMPACT AND HIGH-SPEED OCTAL CLOCK PHASE GENERATOR FOR PHASE INTERPOLATOR APPLICATIONS 审中-公开

    公开(公告)号：US20240313784A1

    公开(公告)日：2024-09-19

    申请号：US18428447

    申请日：2024-01-31

    申请人： ANALOG DEVICES, INC.

    发明人： Rajasekhar Nagulapalli ,  Narendra M.K. Rao

    IPC分类号： H03L7/081 ,  H03K19/017 ,  H03K19/20

    CPC分类号： H03L7/0814 ,  H03K19/01742 ,  H03K19/20

    摘要： Described herein are multi-phase clock generator embodiments for compact octal phase generation for high speed clock. A multi-phase clock generator may comprise an in-phase and quadrature (IQ) clock generator that outputs an intermediate clock signal with quad phases and an octal phase generator that generates an output clock signal comprising one or more octal phases and having a clock frequency same as an input 2-phase clock signal to the multi-phase clock generator. The multi-phase clock generator may incorporate a pull-down circuit and a current bias circuit, which may function to improve phase interpolation linearity of the octal phase generator. Histogram of phase shift error comparison shows significant improvement of a multi-phase clock generator embodiment over conventional phase interpolation.

    Clock and periodic computing machines
    7.
    发明授权
    Clock and periodic computing machines 有权

    公开(公告)号：US12034445B2

    公开(公告)日：2024-07-09

    申请号：US17531788

    申请日：2021-11-21

    申请人： Michael Stephen Fiske

    发明人： Michael Stephen Fiske

    IPC分类号： H04L9/00 ,  G06F21/60 ,  H03K3/0233 ,  H03K19/017 ,  H03K19/14 ,  H03K19/17736

    CPC分类号： H03K19/1774 ,  G06F21/602 ,  H03K3/0233 ,  H03K19/01728 ,  H03K19/14

    摘要： A new computational machine is invented, called a clock machine, that is a novel alternative to computing machines (digital computers) based on logic gates. In an embodiment, computation is performed with one or more clock machines that use time, and can perform any Boolean function. In an embodiment, a cryptographic cipher is implemented with random clock machines, constructed from a non-deterministic process, wherein the compiled set of instructions (i.e., the implementation of the cryptographic procedure) is distinct on each device or chip that executes the cryptographic cipher. In an embodiment, by using a different set of clock machines to execute two different instances of the same cryptographic procedure, each execution of a procedure looks different to malware that may try to infect and subvert the cryptographic procedure. This cryptographic process helps hinder timing attacks. In an embodiment, a detailed implementation of the Midori cipher with random clock machines is described.

    Dual-port SRAM
    9.
    发明授权
    Dual-port SRAM 有权

    公开(公告)号：US12009818B2

    公开(公告)日：2024-06-11

    申请号：US17872445

    申请日：2022-07-25

    申请人： Shanghai Huali Integrated Circuit Corporation

    发明人： Pinhan Chen ,  Chenglei Guo

    IPC分类号： G11C11/412 ,  H03K19/017 ,  H03K19/0944 ,  H03K19/1776

    CPC分类号： H03K19/1776 ,  G11C11/412 ,  H03K19/01721 ,  H03K19/0944

    摘要： The present application discloses a dual-port SRAM having two ports. On a layout, pass gates connecting to the two ports are disposed near pull down transistors of corresponding memory nodes. A cell layout structure of the SRAM cell structure is centrosymmetric. In a first subunit layout structure, a pass gate and a first pull down transistor share the same active region, and an active region of the other pull down transistor is disposed between active regions of the first pull down transistor and a first pull up transistor. The present application improves the symmetry of read paths of the two memory nodes from two ports thus the symmetry of read currents, therefore the variation of the electrical performance of PMOS transistors is reduced and the stability of the electrical performance of the PMOS transistors is improved.

    Bootstrapped switch
    10.
    发明公开
    Bootstrapped switch 审中-公开

    公开(公告)号：US20240171171A1

    公开(公告)日：2024-05-23

    申请号：US18420814

    申请日：2024-01-24

    申请人： REALTEK SEMICONDUCTOR CORPORATION

    发明人： SHIH-HSIUNG HUANG

    IPC分类号： H03K17/06 ,  H03K17/0412 ,  H03K19/017

    CPC分类号： H03K17/063 ,  H03K17/04123 ,  H03K19/01735

    摘要： A bootstrapped switch includes a first transistor, a second transistor, a first capacitor, three switches, and a switch circuit. The switch circuit includes a first switch, a second switch, a second capacitor, and a resistor. The first transistor receives the input voltage and outputs the output voltage. The first terminal of the second transistor receives the input voltage, and the second terminal of the second transistor is coupled to the first terminal of the first capacitor. The control terminal of the first switch receives a clock. The second switch is coupled between the control terminal of the first transistor and the first switch. The second capacitor is coupled between the control terminal of the first switch and the control terminal of the second switch. The resistor is coupled between the control terminal of the second switch and a reference voltage.