发明授权
US5252867A Self-compensating digital delay semiconductor device with selectable
output delays and method therefor
失效
具有可选输出延迟的自补偿数字延迟半导体器件及其方法
- 专利标题: Self-compensating digital delay semiconductor device with selectable output delays and method therefor
- 专利标题(中): 具有可选输出延迟的自补偿数字延迟半导体器件及其方法
-
申请号: US843488申请日: 1992-02-28
-
公开(公告)号: US5252867A公开(公告)日: 1993-10-12
- 发明人: Peter H. Sorrells , Ned D. Garinger
- 申请人: Peter H. Sorrells , Ned D. Garinger
- 申请人地址: CA San Jose
- 专利权人: VLSI Technology, Inc.
- 当前专利权人: VLSI Technology, Inc.
- 当前专利权人地址: CA San Jose
- 主分类号: H03K5/00
- IPC分类号: H03K5/00 ; H03K5/13 ; H03K5/135 ; H03K5/14 ; H03K5/15 ; H03K19/003 ; H03L7/081
摘要:
A self-compensated digital delay semiconductor device is disclosed which uses two identical chains of delay elements. The first chain is the Reference Chain, which is driven by a crystal-controlled digital clock input. The second chain is the Input Signal Delay Chain, which is the delay path for the signal of interest. These two chains are located in physical proximity on the semiconductor die so that variations in manufacturing process, temperature and power supply affect each chain the same. Each of these delay chains is comprised of a series of variable delay elements which are digitally controlled by Monitor Logic, which measures the delay performance of the Reference Chain, and dynamically adjusts the delay of the variable delay elements as induced variations are induced, thereby compensating the delay of the device. Any one of these precise delays can be routed to the output by driving a tap select multiplexer to select the delay of interest. This approach provides precise delays which are constant within a tight tolerance.
公开/授权文献
- US5943516A Camera with a warning system of inappropriate camera holding 公开/授权日:1999-08-24
信息查询