In semiconductor circuits, and particularly in memories, it is often desirable to use bipolar transistors for speed together with MOS elements. However, although the bipolar transistors are useful for speed considerations, they undesirably significantly increase the power consumption of the overall circuit. Accordingly, to reduce power consumption, a bipolar/MOSFET arrangement is provided wherein MOSFETs are used as current sources to supply operation currents to the bipolar transistors only during the periods of their operation. Thus, a semiconductor integrated circuit device is achieved featuring a high operation speed yet consuming reduced amounts of electric power. Additionally, power consumption can be further reduced by providing a time serial operation for actuation of the MOSFETs in different peripheral circuits for a memory array.