公开(公告)号：US07162671B2

公开(公告)日：2007-01-09

申请号：US10918421

申请日：2004-08-16

申请人： Masatoshi Hasegawa ,  Shuichi Miyaoka ,  Hiroshi Akasaki ,  Masahiro Katayama

发明人： Masatoshi Hasegawa ,  Shuichi Miyaoka ,  Hiroshi Akasaki ,  Masahiro Katayama

IPC分类号： G11C29/00

CPC分类号： G11C29/48 ,  G11C11/401 ,  G11C11/41 ,  G11C29/14 ,  G11C29/50 ,  H01L2924/0002 ,  H01L2924/00

摘要： Inputs of a control circuit are connected to a terminal to which an external operation control signal is supplied and a terminal to which a timing signal used exclusively for testing is supplied, and the control circuit is made controllable such that, in a test mode, a state of an internal operation control signal is changed in response to a change of a state of the external operation control signal, and the internal operation control signal is changed in response to the timing exclusively used for testing, whereas, in a normal operation mode, the state of the internal operation control signal is changed in response to the change of the state of the external operation control signal, and the internal operation control signal is changed in response to the change of the external operation control signal.

摘要翻译： 控制电路的输入连接到提供外部操作控制信号的端子和提供专用于测试的定时信号的端子，并且控制电路被制成可控制，使得在测试模式中， 内部操作控制信号的状态响应于外部操作控制信号的状态的改变而改变，并且内部操作控制信号响应于专门用于测试的定时而改变，而在正常操作模式中， 响应于外部操作控制信号的状态的改变而改变内部操作控制信号的状态，并且内部操作控制信号响应于外部操作控制信号的改变而改变。

公开(公告)号：US06735129B2

公开(公告)日：2004-05-11

申请号：US10153525

申请日：2002-05-24

申请人： Hiroshi Akasaki ,  Shuichi Miyaoka ,  Yuji Yokoyama ,  Masatoshi Hasegawa ,  Kozaburo Kurita

发明人： Hiroshi Akasaki ,  Shuichi Miyaoka ,  Yuji Yokoyama ,  Masatoshi Hasegawa ,  Kozaburo Kurita

IPC分类号： G11C700

CPC分类号： G11C7/1066 ,  G11C7/1006 ,  G11C7/1039 ,  G11C7/1072 ,  G11C2207/104

摘要： In a semiconductor integrated circuit device that includes macro cells (circuit blocks that can be designed independently) such as a storage circuit and operates synchronously with an external clock, total delay time from signal input to output is reduced and the speed of operation is increased. In the semiconductor integrated circuit device which has plural circuit blocks coupled in series for signal transmission and whose whole operation is controlled by a clock signal, the semiconductor integrated circuit device including first circuit blocks that receive input signals in response to a first timing signal based on a clock signal, and a second circuit block that forms output signals in response to a second timing signal based on the clock signal, a time difference between the first timing signal and the second timing signal is set to a non-integral multiple of the cycle of the clock signal.

摘要翻译： 在包括诸如存储电路的宏单元（可独立设计的电路块）并且与外部时钟同步地操作的半导体集成电路器件中，从信号输入到输出的总延迟时间减少，并且操作速度增加。 在具有串联耦合用于信号传输并且其整个操作由时钟信号控制的多个电路块的半导体集成电路器件中，半导体集成电路器件包括响应于基于第一定时信号接收输入信号的第一电路块 时钟信号和响应于基于时钟信号的第二定时信号形成输出信号的第二电路块，第一定时信号和第二定时信号之间的时间差被设置为该周期的非整数倍 的时钟信号。

公开(公告)号：US5734616A

公开(公告)日：1998-03-31

申请号：US694059

申请日：1996-08-08

申请人： Hideto Kazama ,  Shuichi Miyaoka ,  Akihiko Emori ,  Kinya Mitsumoto ,  Tomoyuki Someya ,  Masahiro Iwamura ,  Noboru Akiyama

发明人： Hideto Kazama ,  Shuichi Miyaoka ,  Akihiko Emori ,  Kinya Mitsumoto ,  Tomoyuki Someya ,  Masahiro Iwamura ,  Noboru Akiyama

IPC分类号： G11C11/419 ,  G11C7/00

CPC分类号： G11C11/419

摘要： A static RAM includes pre-amplifiers, which are made up solely of emitter-follower transistors having their collectors supplied with the power voltage, in one-to-one correspondence to sub common data line pairs which are connected by column switches to complementary data line pairs of memory arrays. The pre-amplifier is provided with a first switch which turns on during the selected state to connect the sub common data line pair to the bases of the transistors and a second switch which turns on during the unselected state to provide the bases with a certain bias voltage lower than the readout signal voltage on the sub common data line pair. The emitter-follower transistors have their emitters connected commonly to form common emitter lines, which are connected to pairs of input terminals of main amplifiers made up of CMOS transistors.

摘要翻译： 静态RAM包括前置放大器，其仅由具有其电源电压的集电极的射极跟随器晶体管组成，与通过列开关连接到互补数据线的子公共数据线对一一对应 成对的存储器阵列。 前置放大器设置有在选择状态期间导通的第一开关，以将子公共数据线对连接到晶体管的基极;以及第二开关，其在未选择状态期间导通，以向基极提供一定的偏置 电压低于副公共数据线对上的读出信号电压。 射极跟随器晶体管的发射极共同连接形成共同的发射极线，其连接到由CMOS晶体管构成的主放大器的输入端对。

公开(公告)号：US5638335A

公开(公告)日：1997-06-10

申请号：US649166

申请日：1996-05-17

申请人： Noboru Akiyama ,  Seigoh Yukutake ,  Sadayuki Ohkuma ,  Akihiko Emori ,  Takashi Akioka ,  Shuichi Miyaoka ,  Shinji Nakazato ,  Kinya Mitsumoto

发明人： Noboru Akiyama ,  Seigoh Yukutake ,  Sadayuki Ohkuma ,  Akihiko Emori ,  Takashi Akioka ,  Shuichi Miyaoka ,  Shinji Nakazato ,  Kinya Mitsumoto

IPC分类号： G11C11/41 ,  G11C5/00 ,  G06F13/00

CPC分类号： G11C5/06 ,  G11C7/062 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/1078 ,  G11C7/1096

摘要： A memory device comprising a memory array having a plurality of bits, including parity bits, and comprising a plurality of memory blocks, and a bit structure changing section for changing the input/output bits of the memory array, wherein the number of the memory blocks are prescribed to be an integral multiple of three and the input/output bits of the plurality of memory blocks are even. Thereby, the bit structure of the semiconductor memory, having parity bits and which is capable of changing the input/output bits to a plurality of bit structures, can be changed while maintaining the bit structure of the memory blocks even and without increase in propagation delay time.

摘要翻译： 一种存储器件，包括具有多个位的存储器阵列，包括奇偶校验位，并且包括多个存储器块，以及位结构改变部分，用于改变存储器阵列的输入/输出位，其中存储器块的数量 被规定为3的整数倍，并且多个存储块的输入/输出位是偶数。 因此，可以改变具有奇偶校验位并且能够将输入/输出位改变为多个位结构的半导体存储器的位结构，同时保持存储器块的位结构并且不增加传播延迟 时间。

公开(公告)号：US5111432A

公开(公告)日：1992-05-05

申请号：US492329

申请日：1990-03-12

申请人： Shuichi Miyaoka

发明人： Shuichi Miyaoka

IPC分类号： G11C11/414 ,  G11C7/00 ,  G11C7/10 ,  G11C11/34 ,  G11C11/413 ,  G11C11/419

CPC分类号： G11C7/1057 ,  G11C11/413 ,  G11C7/00 ,  G11C7/1051

摘要： In semiconductor circuits, and particularly in memories, it is often desirable to use bipolar transistors for speed together with MOS elements. However, although the bipolar transistors are useful for speed considerations, they undesirably significantly increase the power consumption of the overall circuit. Accordingly, to reduce power consumption, a bipolar/MOSFET arrangement is provided wherein MOSFETs are used as current sources to supply operation currents to the bipolar transistors only during the periods of their operation. Thus, a semiconductor integrated circuit device is achieved featuring a high operation speed yet consuming reduced amounts of electric power. Additionally, power consumption can be further reduced by providing a time serial operation for actuation of the MOSFETs in different peripheral circuits for a memory array.

摘要翻译： 在半导体电路中，特别是在存储器中，通常希望与MOS元件一起使用双极晶体管。 然而，虽然双极晶体管对于速度考虑是有用的，但是它们不利地显着增加了整个电路的功耗。 因此，为了降低功耗，提供了一种双极/ MOSFET布置，其中MOSFET仅在其工作期间用作电流源以向双极型晶体管提供工作电流。 因此，实现了具有高操作速度但消耗减少的电力量的半导体集成电路器件。 此外，通过提供用于在用于存储器阵列的不同外围电路中的MOSFET的驱动的时间串行操作，可以进一步降低功耗。

公开(公告)号：US07023749B2

公开(公告)日：2006-04-04

申请号：US11040030

申请日：2005-01-24

申请人： Masatoshi Hasegawa ,  Shuichi Miyaoka

发明人： Masatoshi Hasegawa ,  Shuichi Miyaoka

IPC分类号： G11C7/00

CPC分类号： G11C7/1069 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/12 ,  G11C11/4076 ,  G11C2207/2281

摘要： The present invention provides a semiconductor integrated circuit device equipped with a memory circuit, which realizes speeding up of its operation in a simple configuration or realizes high reliability and enhancement of product yields in a simple configuration. A memory cell is selected from within a memory array having a plurality of memory cells by a selector or selection circuit. MOSFETs constituting a precharge circuit provided for signal lines for transferring a read signal therefrom to a main amplifier are respectively brought to an on state based on a memory cell select start signal transferred to the selection circuit and brought to an off state prior to the transfer of the read signal from the memory cell to thereby complete precharging, whereby NBTI degradation at standby is avoided.

公开(公告)号：US20050162969A1

公开(公告)日：2005-07-28

申请号：US11040030

申请日：2005-01-24

申请人： Masatoshi Hasegawa ,  Shuichi Miyaoka

发明人： Masatoshi Hasegawa ,  Shuichi Miyaoka

IPC分类号： G11C11/41 ,  G11C7/10 ,  G11C7/12 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/409 ,  G11C8/00

CPC分类号： G11C7/1069 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/12 ,  G11C11/4076 ,  G11C2207/2281

摘要： The present invention provides a semiconductor integrated circuit device equipped with a memory circuit, which realizes speeding up of its operation in a simple configuration or realizes high reliability and enhancement of product yields in a simple configuration. A memory cell is selected from within a memory array having a plurality of memory cells by a selector or selection circuit. MOSFETs constituting a precharge circuit provided for signal lines for transferring a read signal therefrom to a main amplifier are respectively brought to an on state based on a memory cell select start signal transferred to the selection circuit and brought to an off state prior to the transfer of the read signal from the memory cell to thereby complete precharging, whereby NBTI degradation at standby is avoided.

摘要翻译： 本发明提供一种配备有存储电路的半导体集成电路器件，其以简单的配置实现其操作的加速或者以简单的配置实现高可靠性和产品产量的提高。 通过选择器或选择电路从具有多个存储单元的存储器阵列内选择存储单元。 构成为将用于将读取信号传送到主放大器的信号线的预充电电路的MOSFET分别基于传送到选择电路的存储单元选择开始信号而变为导通状态，并且在转移 来自存储器单元的读取信号从而完成预充电，从而避免在待机时NBTI退化。

公开(公告)号：US06794678B2

公开(公告)日：2004-09-21

申请号：US10058787

申请日：2002-01-30

申请人： Masatoshi Hasegawa ,  Shuichi Miyaoka ,  Hiroshi Akasaki ,  Masahiro Katayama

发明人： Masatoshi Hasegawa ,  Shuichi Miyaoka ,  Hiroshi Akasaki ,  Masahiro Katayama

IPC分类号： G11C2900

CPC分类号： G11C29/48 ,  G11C11/401 ,  G11C11/41 ,  G11C29/14 ,  G11C29/50 ,  H01L2924/0002 ,  H01L2924/00

摘要： Inputs of a control circuit are connected to a terminal to which an external operation control signal is supplied and a terminal to which a timing signal used exclusively for testing is supplied, and the control circuit is made controllable such that, in a test mode, a state of an internal operation control signal is changed in response to a change of a state of the external operation control signal, and the internal operation control signal is changed in response to the timing exclusively used for testing, whereas, in a normal operation mode, the state of the internal operation control signal is changed in response to the change of the state of the external operation control signal, and the internal operation control signal is changed in response to the change of the external operation control signal.

摘要翻译： 控制电路的输入连接到提供外部操作控制信号的端子和提供专用于测试的定时信号的端子，并且控制电路被制成可控制，使得在测试模式中， 内部操作控制信号的状态响应于外部操作控制信号的状态的改变而改变，并且内部操作控制信号响应于专门用于测试的定时而改变，而在正常操作模式中， 响应于外部操作控制信号的状态的改变而改变内部操作控制信号的状态，并且内部操作控制信号响应于外部操作控制信号的改变而改变。

公开(公告)号：US5373474A

公开(公告)日：1994-12-13

申请号：US124582

申请日：1993-09-22

申请人： Shuichi Miyaoka

发明人： Shuichi Miyaoka

IPC分类号： G11C7/00 ,  G11C7/10 ,  G11C11/413

CPC分类号： G11C7/1057 ,  G11C11/413 ,  G11C7/00 ,  G11C7/1051

摘要： In semiconductor circuits, and particularly in memories, it is often desirable to use bipolar transistors for speed together with MOS elements. However, although the bipolar transistors are useful for speed considerations, they undesirably significantly increase the power consumption of the overall circuit. Accordingly, to reduce power consumption, a bipolar/MOSFET arrangement is provided wherein MOSFETs are used as current sources to supply operation currents to the bipolar transistors only during the periods of their operation. Thus, a semiconductor integrated circuit device is achieved featuring a high operation speed yet consuming reduced amounts of electric power. Additionally, power consumption can be further reduced by providing a time serial operation for actuation of the MOSFETs in different peripheral circuits for a memory array.

摘要翻译： 在半导体电路中，特别是在存储器中，通常希望与MOS元件一起使用双极晶体管。 然而，虽然双极晶体管对于速度考虑是有用的，但是它们不利地显着增加了整个电路的功耗。 因此，为了降低功耗，提供了一种双极/ MOSFET布置，其中MOSFET仅在其工作期间用作电流源以向双极型晶体管提供工作电流。 因此，实现了具有高操作速度但消耗减少的电力量的半导体集成电路器件。 此外，通过提供用于在用于存储器阵列的不同外围电路中的MOSFET的驱动的时间串行操作，可以进一步降低功耗。

公开(公告)号：US20110049988A1

公开(公告)日：2011-03-03

申请号：US12855428

申请日：2010-08-12

申请人： Nobuyasu KANEKAWA ,  Teppei HIROTSU ,  Itaru TANABE ,  Shuichi MIYAOKA ,  Ryoichi OURA

发明人： Nobuyasu KANEKAWA ,  Teppei HIROTSU ,  Itaru TANABE ,  Shuichi MIYAOKA ,  Ryoichi OURA

IPC分类号： H02J4/00

CPC分类号： G05F1/46 ,  B60L2240/441 ,  B60L2240/445 ,  B60L2240/486 ,  B60W2510/0638 ,  B60W2510/0676 ,  B60W2540/10 ,  B60W2540/16 ,  Y10T307/445

摘要： The present invention aims to provide a control system which is capable of building high-precision current detecting means in a single-chip LSI and can be realized at a lower cost, and a semiconductor device used in the control system. Drive circuits are provided inside the same semiconductor chip. The drive circuits are equipped with: current detecting shunt resistors each of which is provided in each of the drive circuits and detects a current flowing through a load, the current detecting shunt resistors being provided within a semiconductor chip by the same process; a dummy resistor provided within the semiconductor chip by the same process as the current detecting shunt resistors; and a calibration reference externally attached to the semiconductor chip and connected to the dummy resistor. A correcting means corrects the values of currents that flow through the current detecting shunt resistors, using the dummy resistor and the calibration reference.

摘要翻译： 本发明旨在提供一种能够在单芯片LSI中构建高精度电流检测装置并且可以以较低成本实现的控制系统以及在控制系统中使用的半导体装置。 驱动电路设置在同一半导体芯片的内部。 驱动电路配备有电流检测分流电阻器，每个驱动电路设置在每个驱动电路中并检测流过负载的电流，电流检测分流电阻器通过相同的工艺设置在半导体芯片内; 通过与电流检测分流电阻器相同的工艺在半导体芯片内提供虚拟电阻器; 以及外部附接到半导体芯片并连接到虚拟电阻器的校准参考。 校正装置使用虚拟电阻器和校准基准校正流过电流检测分流电阻器的电流值。