A linear predictive ADC employs a fully feed forward design to extend its dynamic range, allow greater speed of operation, achieve stable operation and eliminate a requirement for sample-and-hold circuits. A first quantizer (Qc) converts an input analog signal to a digital format, while a signal predictor (32) predicts a subsequent value of the input signal. After conversion back to analog format, the predicted signal is compared with the actual subsequent value of the input signal to produce an error signal that is converted to a digital format by a second quantizer (Qf). The digital predicted signal is fed forward and combined with the digital error signal to produce a high precision digital output. The analog error signal is preferably amplified prior to digitation to take advantage of the full bit capacity of the second quanitzer (Qf), and then digitally de-amplified back to its original scale. Digital gain and offset adjustment mechanisms (44, 50) are preferably provided to compensate for amplification/de-amplification mismatches and system offsets. The quantizers (Qc, Qf), predictor (32) and a digital register (36) that interfaces between the predictor and the output combiner (46) are clocked in a set sequence to ensure that the predicted signal from the register (36) corresponds in time to the error signal presented to the output combiner (46).