A multicomputer chip has a common bus and up to ten microcomputers connected in parallel to the common bus via routers contained in the microcomputers. The common bus can be connected to an external bus by means of a router mounted on or off the chip. Any defective computer found during testing can be rendered inactive by assigning it an unused address and, in this way, the remaining computers are unaffected. Instead of providing each multicomputer on a separate chip, a complete wafer may be manufactured so that it contains many of the multicomputers. A hierarchical bus system interconnects the multicomputers so as to permit efficient routing of data between the various computers.