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    Parallel microprocessor architecture
    3.
    发明授权
    Parallel microprocessor architecture 失效
    并行微处理器架构

    公开(公告)号：US5276893A

    公开(公告)日：1994-01-04

    申请号：US310828

    申请日：1989-02-08

    Applicant: Yvon Savaria

    Inventor： Yvon Savaria

    IPC: G06F11/00 ,  G06F15/80 ,  G11C29/00 ,  G06F15/20

    CPC classification number: G06F11/181 ,  G06F11/184 ,  G06F15/8015 ,  G11C29/006

    Abstract: A multicomputer chip has a common bus and up to ten microcomputers connected in parallel to the common bus via routers contained in the microcomputers. The common bus can be connected to an external bus by means of a router mounted on or off the chip. Any defective computer found during testing can be rendered inactive by assigning it an unused address and, in this way, the remaining computers are unaffected. Instead of providing each multicomputer on a separate chip, a complete wafer may be manufactured so that it contains many of the multicomputers. A hierarchical bus system interconnects the multicomputers so as to permit efficient routing of data between the various computers.

    Abstract translation: 多计算机芯片具有公共总线和多达10个微型计算机，通过微型计算机中包含的路由与公共总线并联连接。 公共总线可以通过安装在芯片上或者芯片上的路由器连接到外部总线。 在测试期间发现的任何有缺陷的计算机都可以通过为其分配未使用的地址而变得无效，并且以这种方式，剩余的计算机不受影响。 代替在单独的芯片上提供每个多计算机，可以制造完整的晶片，使得其包含许多多计算机。 分层总线系统互连多计算机，以便允许在各种计算机之间有效地路由数据。

    Tunable Semiconductor Component Provided with a Current Barrier
    4.
    发明申请
    Tunable Semiconductor Component Provided with a Current Barrier 审中-公开
    带有电流屏障的可调谐半导体元件

    公开(公告)号：US20100084737A1

    公开(公告)日：2010-04-08

    申请号：US12087767

    申请日：2007-01-17

    Applicant: Alain Lacourse ,  Mathieu Ducharme ,  Hugo St-Jean ,  Yves Gagnon ,  Yvon Savaria ,  Michel Meunier

    Inventor： Alain Lacourse ,  Mathieu Ducharme ,  Hugo St-Jean ,  Yves Gagnon ,  Yvon Savaria ,  Michel Meunier

    IPC: H01L23/525 ,  H01L29/06

    CPC classification number: H01L23/647 ,  H01L21/02697 ,  H01L27/08 ,  H01L29/0646 ,  H01L29/0692 ,  H01L29/8605 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: This invention pertains to a color coatings blender apparatus to be used for color composition customization for the application of color coatings on 2D and 3D surfaces. The apparatus is comprised of a main body and interchangeable inserts all with central blender chambers and primary and secondary ports, and interchangeable spindles; the configurations of which are governed by coating technical characteristics. This invention integrates gradient specific programmable computer digital processes to function as internal editors, manipulate information and present the operator with multiple options and production overrides. This invention will make data analysis more interactive by utilizing existing external software applications as editors and expanding the process of visual communications for multiple purposes. While the blender apparatus, complete with external selectable appurtenances, can be used manually, it can also be combined with a programmable computer for producing physical gradient layers.

    Abstract translation: 本发明涉及用于在2D和3D表面上应用彩色涂层的颜色组合物定制的彩色涂料混合器装置。 该设备包括主体和可互换的插入件，全部具有中心搅拌器室和主要和次要端口以及可互换的主轴; 其结构由涂层技术特性决定。 本发明集成梯度专用可编程计算机数字处理功能，作为内部编辑器，操纵信息并向操作员呈现多种选项和生产覆盖。 本发明将通过利用现有的外部软件应用程序作为编辑器，并扩展视觉通信的过程，从而实现数据分析的更多交互。 虽然可以手动使用具有外部可选附件的搅拌机，但也可以与用于生产物理梯度层的可编程计算机组合使用。

    Multi-equalization method and apparatus
    5.
    发明授权
    Multi-equalization method and apparatus 有权
    多均衡方法和装置

    公开(公告)号：US07693490B2

    公开(公告)日：2010-04-06

    申请号：US11690468

    申请日：2007-03-23

    Applicant: François Gagnon ,  Yvon Savaria ,  Philippe Dumais ,  Mohamed Lassaad Ammari ,  Claude Thibeault

    Inventor： François Gagnon ,  Yvon Savaria ,  Philippe Dumais ,  Mohamed Lassaad Ammari ,  Claude Thibeault

    IPC: H04B1/00

    CPC classification number: H04L25/03006 ,  H04B3/14 ,  H04B7/005 ,  H04L2025/03535 ,  H04L2025/03726

    Abstract: A method and apparatus is disclosed for performing a multi-equalization of a transmitted signal on a channel having varying characteristics comprising equalizing the transmitted signal using a plurality of setting defining a plurality of equalizing functions to provide a corresponding plurality of symbol signal, synchronizing each of the plurality of symbol signals to provide a plurality of synchronized signals, selecting at least one of the plurality of synchronized signals according to at least one transmission performance criterion and providing the selected one of the plurality of synchronized signals.

    Abstract translation: 公开了一种用于在具有变化特性的信道上执行发送信号的多均衡的方法和装置，包括使用定义多个均衡函数的多个设置来均衡发送信号，以提供对应的多个符号信号， 所述多个符号信号提供多个同步信号，根据至少一个传输性能标准选择所述多个同步信号中的至少一个，并提供所述多个同步信号中选择的一个。

    Method for modifying the impedance of semiconductor devices using a focused heating source
    6.
    发明申请
    Method for modifying the impedance of semiconductor devices using a focused heating source 有权
    使用聚焦加热源修改半导体器件的阻抗的方法

    公开(公告)号：US20050186766A1

    公开(公告)日：2005-08-25

    申请号：US11088720

    申请日：2005-03-25

    Applicant: Alain Lacourse ,  Hugues Langlois ,  Yvon Savaria ,  Yves Gagnon

    Inventor： Alain Lacourse ,  Hugues Langlois ,  Yvon Savaria ,  Yves Gagnon

    IPC: H01L27/04 ,  H01C17/26 ,  H01L21/02 ,  H01L21/22 ,  H01L21/268 ,  H01L21/324 ,  H01L21/329 ,  H01L21/768 ,  H01L21/822 ,  H01L27/08 ,  H01L21/4763

    CPC classification number: H01L28/20 ,  H01C17/26 ,  H01L21/268 ,  H01L21/324 ,  H01L21/76894 ,  H01L27/0802 ,  H01L29/66166

    Abstract: A method is provided for tuning (i.e. modifying, changing) the impedance of semiconductor components or devices using a focused heating source. The method may be exploited for finely tuning the impedance of semiconductor components or devices, by modifying the dopant profile of a region of low dopant concentration (i.e. increasing the dopant concentration) by diffusion of dopants from adjacent regions of higher dopant concentration through the melting action of a focused heating source, for example a laser. The present invention is in particular directed to the use of lasers in relation to circuits for the creation of conductive links and pathways where none existed before. The present invention more particularly relates to a means wherein impedance modification (i.e. trimming or tuning) may advantageously be carried out as a function of the location of one or more conductive bridge(s) along the length of a gap region.

    Abstract translation: 提供了一种用于使用聚焦加热源来调谐（即修改，改变）半导体部件或器件的阻抗的方法。 该方法可用于微调半导体组件或器件的阻抗，通过通过掺杂剂从较高掺杂剂浓度的相邻区域扩散通过熔融作用来改变掺杂剂浓度低的区域的掺杂剂分布（即增加掺杂剂浓度） 的聚焦加热源，例如激光。 本发明特别涉及激光器相对于用于创建之前不存在的导电链路和路径的电路的使用。 本发明更具体地涉及一种其中阻抗修改（即修整或调谐）可以有利地作为沿着间隙区域的长度的一个或多个导电桥的位置的函数来执行的装置。

    Fault tolerant scan chain for a parallel processing system
    7.
    发明授权
    Fault tolerant scan chain for a parallel processing system 失效
    用于并行处理系统的容错扫描链

    公开(公告)号：US06928606B2

    公开(公告)日：2005-08-09

    申请号：US10323896

    申请日：2002-12-20

    Applicant: Yvon Savaria ,  Meng Lu

    Inventor： Yvon Savaria ,  Meng Lu

    IPC: G01R31/3185 ,  G06F11/08 ,  G01R31/28

    CPC classification number: G01R31/318536

    Abstract: A highly robust fault tolerant scan chain is designed for scanning (and/or controlling a configuration of) a parallel processing system. The scan chain implements parallel redundant scan chains that follow physically diverse paths through the parallel processing system. For each IC under test, a set of redundant TAPs perform a boundary scan, and the test results are combined by voting. The TAPs of each set are physically diverse, in that they are physically located in separate power domains of the parallel processing system. As a result, the scan chain is robust to faults affecting power and/or control signal supply to any one power domain. Respective input and output dummy cells at opposite extreme ends of the scan chain provide a graceful separation and recombination of the redundant parallel scan chains, and so renders the architecture of the scan chain transparent to external boundary scan circuit elements.

    Abstract translation: 高度鲁棒的容错扫描链被设计用于扫描（和/或控制）并行处理系统的配置。 扫描链实现并行冗余扫描链，其跟随物理上不同的路径通过并行处理系统。 对于被测试的每个IC，一组冗余TAP执行边界扫描，并通过投票结合测试结果。 每组的TAP在物理上是不同的，因为它们物理上位于并行处理系统的独立电源域中。 因此，扫描链对于影响到任何一个电源域的功率和/或控制信号供应的故障都是稳健的。 扫描链相对端的相应输入和输出虚拟单元提供冗余并行扫描链的优雅分离和复合，从而使扫描链的架构对外部边界扫描电路元件透明。

    MULTI-EQUALIZATION METHOD AND APPARATUS
    10.
    发明申请
    MULTI-EQUALIZATION METHOD AND APPARATUS 有权
    多均衡方法和装置

    公开(公告)号：US20070293147A1

    公开(公告)日：2007-12-20

    申请号：US11690468

    申请日：2007-03-23

    Applicant: Francois Gagnon ,  Yvon Savaria ,  Philippe Dumais ,  Mohamed Ammari ,  Claude Thibeault

    Inventor： Francois Gagnon ,  Yvon Savaria ,  Philippe Dumais ,  Mohamed Ammari ,  Claude Thibeault

    IPC: H04H7/00

    CPC classification number: H04L25/03006 ,  H04B3/14 ,  H04B7/005 ,  H04L2025/03535 ,  H04L2025/03726

    Abstract: A method and apparatus is disclosed for performing a multi-equalization of a transmitted signal on a channel having varying characteristics comprising equalizing the transmitted signal using a plurality of setting defining a plurality of equalizing functions to provide a corresponding plurality of symbol signal, synchronizing each of the plurality of symbol signals to provide a plurality of synchronized signals, selecting at least one of the plurality of synchronized signals according to at least one transmission performance criterion and providing the selected one of the plurality of synchronized signals.

    Abstract translation: 公开了一种用于在具有变化特性的信道上执行发送信号的多均衡的方法和装置，包括使用定义多个均衡函数的多个设置来均衡发送信号，以提供对应的多个符号信号， 所述多个符号信号提供多个同步信号，根据至少一个传输性能标准选择所述多个同步信号中的至少一个，并提供所述多个同步信号中选择的一个。

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