Invention Grant
US5279982A Method for fabricating memory cell matrix having parallel source and drain interconnection metal lines formed on the substrate and topped by orthogonally oriented gate interconnection parallel metal lines 失效
用于制造具有平行的源极和漏极互连金属线的存储单元矩阵的方法,所述金属线形成在所述衬底上并且由正交定向的栅极互连并行金属线

Method for fabricating memory cell matrix having parallel source and
drain interconnection metal lines formed on the substrate and topped by
orthogonally oriented gate interconnection parallel metal lines
Abstract:
A cell array for EPROM or ROM type memories has drain and source interconnection metal lines connecting in common drain and source regions, respectively, of the cells arranged on a same row of the array formed directly on the semiconductor substrate, superimposed at crossings to uninterrupted isolation strips formed on the semiconductor substrate for separating cells belonging to two adjacent columns of the array, and gate interconnection lines (WORD LINES), connecting the control gate electrodes of cells arranged on a same column, which run parallel to and between said isolation strips and superimposed at crossings to said underlying source and drain lines (BIT LINES). The array is markedly more compact than an array made according to the prior art though utilizing fabrication apparatuses with similar optical resolution, while maximizing the source and drain contact areas of the cells. In ROM devices, the customizing may advantageously take place during the final steps of the fabrication process by means of a gate contact mask having a reduced criticality in respect to a comparable drain contact mask used in prior art processes. The fabrication process employs self-alignment techniques and masks with a relatively low alignment criticality.
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