公开(公告)号：US5210046A

公开(公告)日：1993-05-11

申请号：US632101

申请日：1990-12-20

Applicant: Pier L. Crotti

Inventor： Pier L. Crotti

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/11517 ,  H01L27/115

Abstract: An integrated EPROM device which can be manufactured using standard high definition photolithographic techniques with unit cells of markedly reduced dimensions as compared to the minimum dimensions that can be achieved with the prior art, has field isolation structures between adjacent cells along rows of the array in the form of continuous isolation strips which extend for the whole column length of the array, thus avoiding the problems associated with photolithographic defining rectangular geometries. The electrical interconnection between the sources of the cells of each row is achieved by a special metal source "line", formed between two adjacent gate lines, using for the purpose a conformally deposited metal layer from which both the drain contacts and these source interconnection metal "lines" are created in a self-alignment way.

公开(公告)号：US5345417A

公开(公告)日：1994-09-06

申请号：US016741

申请日：1993-02-11

Applicant: Pier L. Crotti

Inventor： Pier L. Crotti

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/40

CPC classification number: H01L27/11517 ,  H01L27/115

Abstract: An integrated EPROM device which can be manufactured using standard high-definition photolithographic techniques with unit cells of markedly reduced dimensions as compared to the minimum dimensions that can be achieved with the prior art, has field isolation structures between adjacent cells along rows of the array in the form of continuous isolation strips which extend for the whole column length of the array, thus avoiding the problems associated with photolithographic defining rectangular geometries. The electrical interconnection between the sources of the cells of each row is achieved by a special metal source "line" formed between two adjacent gate lines, using for the purpose a conformally deposited metal layer from which both the drain contacts and these source interconnection metal "lines" are created in a self-alignment way.

Abstract translation: 可以使用标准高清晰度光刻技术制造的集成EPROM器件，其具有与现有技术可以实现的最小尺寸相比具有明显减小的尺寸的单元电池，具有沿着阵列行的相邻单元之间的场隔离结构 连续隔离带的形式，其延伸到阵列的整个列长度，从而避免与光刻定义矩形几何相关的问题。 通过在两个相邻的栅极线之间形成的特殊的金属源“线”来实现每一行的电池单元之间的电互连，为了这个目的，为了共同沉积的金属层，漏极接触和这些源互连金属“ 线条“以自对准方式创建。

公开(公告)号：US5332470A

公开(公告)日：1994-07-26

申请号：US149707

申请日：1993-11-09

Applicant: Pier L. Crotti

Inventor： Pier L. Crotti

IPC: H01L21/66 ,  G03F7/00 ,  G03F7/20 ,  H01L21/027 ,  H01L21/306 ,  B44C1/22 ,  C03C15/00 ,  C03C25/06

CPC classification number: G03F7/70633 ,  G03F7/0035 ,  Y10S438/975

Abstract: Process for the manufacture of calibration structures particularly for the calibration of machines for measuring alignment in integrated circuits in general, the peculiarity of which consists in the fact that calibration structures are provided in which the alignment of one layer with respect to another layer is set to a known extent by means of a single masking.

Abstract translation: 用于制造校准结构的方法，特别是用于校准用于在集成电路中测量对准的机器，其特征在于提供校准结构，其中一层相对于另一层的对准被设置为 已知的程度通过一个单一的掩蔽。

公开(公告)号：US5068202A

公开(公告)日：1991-11-26

申请号：US448883

申请日：1989-12-12

Applicant: Pier L. Crotti ,  Nadia Iazzi

Inventor： Pier L. Crotti ,  Nadia Iazzi

IPC: H01L21/76 ,  H01L21/308 ,  H01L21/32 ,  H01L21/762

CPC classification number: H01L21/32 ,  H01L21/3086 ,  H01L21/76232 ,  H01L21/76237 ,  Y10S438/944 ,  Y10S438/978

Abstract: Encased (BOX) trench insolation structures in a silicon substrate are formed by firstly RIE etching an ONO multilayer (Oxide-Nitrite-Oxide) formed on the surface of a monocrystalline silicon substrate through a mask defining the active areas until exposing the silicon. A successive deposition of a conformable TEOS oxide layer followed by a "blanket" RIE etching, leave tapered "spacers" on the vertical etched flanks of the ONO multilayer. Through such a self-aligned "aperture" an isotropic plasma etching (round-etch) of the silicon is performed until the lateral, under-cut, etch front below the oxide spacers reaches the bottom layer of the isolation area defining etching previously conducted through the ONO multilayer. The peculiarities of the round-etch profile are thus fully exploited for more easily implanting the walls and bottom of the trench and avoiding the presence of electric field affecting sharp corners. The process maintains a precise lateral dimensional control and does not require special high resolution apparatuses.

公开(公告)号：US5279982A

公开(公告)日：1994-01-18

申请号：US734503

申请日：1991-07-23

Applicant: Pier L. Crotti

Inventor： Pier L. Crotti

IPC: H01L21/8247 ,  H01L21/8246 ,  H01L27/112 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/265

CPC classification number: H01L27/115

Abstract: A cell array for EPROM or ROM type memories has drain and source interconnection metal lines connecting in common drain and source regions, respectively, of the cells arranged on a same row of the array formed directly on the semiconductor substrate, superimposed at crossings to uninterrupted isolation strips formed on the semiconductor substrate for separating cells belonging to two adjacent columns of the array, and gate interconnection lines (WORD LINES), connecting the control gate electrodes of cells arranged on a same column, which run parallel to and between said isolation strips and superimposed at crossings to said underlying source and drain lines (BIT LINES). The array is markedly more compact than an array made according to the prior art though utilizing fabrication apparatuses with similar optical resolution, while maximizing the source and drain contact areas of the cells. In ROM devices, the customizing may advantageously take place during the final steps of the fabrication process by means of a gate contact mask having a reduced criticality in respect to a comparable drain contact mask used in prior art processes. The fabrication process employs self-alignment techniques and masks with a relatively low alignment criticality.

Abstract translation: 用于EPROM或ROM型存储器的单元阵列具有分别连接在布置在直接形成在半导体衬底上的阵列的同一行上的单元的公共漏极和源极区域中的漏极和源极互连金属线，在交叉处叠加到不间断隔离 形成在半导体衬底上的用于分离属于阵列的两个相邻列的单元的栅极和栅极互连线（WORD LINES），栅极互连线（WORD LINES）连接布置在同一列上的单元的控制栅极电极，该栅极互连线平行于所述隔离带和 在交叉处叠加到所述底层源极和漏极线（BIT LINES）。 该阵列显着地比根据现有技术制成的阵列更紧凑，尽管利用具有类似光学分辨率的制造装置，同时使单元的源极和漏极接触面积最大化。 在ROM器件中，定制可以有利地在制造工艺的最后步骤期间通过相对于现有技术工艺中使用的类似漏极接触掩模具有降低的临界性的栅极接触掩模进行。 制造工艺采用自对准技术和具有较低对准关键性的掩模。

公开(公告)号：US5227014A

公开(公告)日：1993-07-13

申请号：US435890

申请日：1989-11-14

Applicant: Pier L. Crotti ,  Nadia Iazzi

Inventor： Pier L. Crotti ,  Nadia Iazzi

IPC: H01L21/3213 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/768

CPC classification number: H01L21/76804 ,  H01L21/31116

Abstract: Step coverage in contacts may be improved by forming a tapered hole through a dielectric layer by:a) plasma (RIE) etching through a "contact" mask the dielectric for a depth shorter than the thickness of the layer leaving a residual thickness of dielectric on the bottom of the etch;b) removing the residual masking material;c) conformally depositing a TEOS layer;d) etching the conformally deposited TEOS layer without a mask in (RIE) plasma until exposing the underlying silicon or polysilicon with which the contact must be established.The anisotropic etching of the TEOS layer, conformally deposited on the partially pre-etched dielectric layer, determines a "self-aligned" exposition of the underlying silicon or polysilicon and leaves a tapered TEOS residue on the vertical pre-etched hole's walls, thus providing a desired tapering of the contact hole. Photolithographic definition is no longer a critical factor.

公开(公告)号：US4966867A

公开(公告)日：1990-10-30

申请号：US424446

申请日：1989-10-20

Applicant: Pier L. Crotti ,  Nadia Iazzi

Inventor： Pier L. Crotti ,  Nadia Iazzi

IPC: H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L21/60 ,  H01L21/768 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L21/76897 ,  H01L21/28525 ,  H01L21/76819 ,  Y10S438/911 ,  Y10S438/978

Abstract: A process for forming self-aligned metal-semiconductor contacts in integrated MISFET devices determining during a phase of the fabrication the presence on the surface of a wafer of parallel gate lines of polycrystalline silicon provided with lateral "spacers", is founded on the formation of a dielectric oxide layer of a differentiated thickness, having a reduced thickness on the bottom of the valley between two adjacent gate lines wherein the contacts must be formed. The method comprises conformably depositing a first layer of dielectric silicon oxide, a second layer of precursor polycrystalline silicon and a third layer of nitride, followed by depositing a layer of planarization SOG. By blanket etching the SOG layer and the nitride layer, the crests of the precursor polycrystalline silicon layer are exposed. A residual layer of nitride is left inside the valley between adjacent gate lines. The precursor layer of polycrystalline silicon is thermally converted in the areas unmasked by the residual nitride into a dielectric silicon oxide and the removal from the bottom of valleys of the residual nitride and of the residual precursor polycrystalline silicon leaves the front of the wafer covered by a dielectric layer having the desired differentiated thickness, i.e. thinn (corresponding to the thickness of the first conformably deposited oxide layer) on the bottom of valleys between gate lines. By means of a noncritical mask the "length" of the self-aligned contacts is defined and the layer of dielectric is etched until exposing the semiconductor in contact areas along the bottom of the valleys between two adjacent parallel gate lines.

公开(公告)号：US4957881A

公开(公告)日：1990-09-18

申请号：US424450

申请日：1989-10-20

Applicant: Pier L. Crotti

Inventor： Pier L. Crotti

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/60 ,  H01L21/768 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L21/76897 ,  H01L21/76885 ,  Y10S438/978

Abstract: A process for forming self-aligned metal-semiconductor contacts in a device comprising MISFET type structures essentially comprises conformably depositing a matrix metallic layer on the front of the wafer and the subsequent deposition of a planarization SOG layer. After having used a noncritical mask for defining the "length" of the selfaligned contacts to be formed, the SOG layer is etched until leaving a residue layer on the bottom of the valleys of the conformably deposited matrix metallic layer in areas between two adjacent gate lines of polysilicon. A selective etching of the matrix layer using said SOG residues as a mask, defines the contacts, self-aligned in respect to the opposite spacers of two adjacent polysilicon gate lines. An insulating dielectric layer is deposited and etched until exposing the peaks of the preformed contacts. Over such an advantageously planarized surface contacts on the polysilicon gate lines may be defined by a customary masking process and finally the second level metal is deposited.