Invention Grant
- Patent Title: High-speed semicondustor memory integrated circuit arrangement having power and signal lines with reduced resistance
- Patent Title (中): 高速半导体存储器集成电路布置具有功率和信号线,电阻降低
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Application No.: US695983Application Date: 1991-05-06
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Publication No.: US5280450APublication Date: 1994-01-18
- Inventor: Yoshinobu Nakagome , Eiji Kume , Kiyoo Itoh , Hitoshi Tanaka
- Applicant: Yoshinobu Nakagome , Eiji Kume , Kiyoo Itoh , Hitoshi Tanaka
- Applicant Address: JPX Tokyo JPX Tokyo
- Assignee: Hitachi, Ltd.,Hitachi VLSI Engineering Corporation
- Current Assignee: Hitachi, Ltd.,Hitachi VLSI Engineering Corporation
- Current Assignee Address: JPX Tokyo JPX Tokyo
- Priority: JPX2-121334 19900514
- Main IPC: G11C5/14
- IPC: G11C5/14 ; G11C7/06 ; G11C7/10 ; G11C11/40
Abstract:
A semiconductor integrated circuit is disclosed, in which a group of sense amplifiers activated at the same time by a selection signal on a selection signal line are divided into a plurality of blocks, and a power-source line for driving sense amplifiers is formed for each sense amplifier block so as to cross the selection signal line. Alternatively, an input/output line is divided into a plurality of sub-input/output lines, and a plurality of input/output lines are formed so that each input/output line crosses its sub-input/output lines, to form a hierarchical structure with respect to input/output lines. Thus, the load capacitance of each power-source line is reduced, and the time constant of each of the charging and discharging of the load capacitance is decreased. That is, the above semiconductor integrated circuit can operate at high speed.
Public/Granted literature
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