发明授权
US5287467A Pipeline for removing and concurrently executing two or more branch
instructions in synchronization with other instructions executing in
the execution unit
失效
用于与在执行单元中执行的其他指令同步地去除并同时执行两个或更多个分支指令的流水线
- 专利标题： Pipeline for removing and concurrently executing two or more branch instructions in synchronization with other instructions executing in the execution unit
- 专利标题（中）： 用于与在执行单元中执行的其他指令同步地去除并同时执行两个或更多个分支指令的流水线
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申请号： US687309申请日： 1991-04-18
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公开(公告)号： US5287467A公开(公告)日： 1994-02-15
- 发明人: Bartholomew Blaner , Thomas L. Jeremiah , Stamatis Vassiliadis , Phillip G. Williams
- 申请人： Bartholomew Blaner , Thomas L. Jeremiah , Stamatis Vassiliadis , Phillip G. Williams
- 申请人地址： NY Armonk
- 专利权人： International Business Machines Corporation
- 当前专利权人： International Business Machines Corporation
- 当前专利权人地址： NY Armonk
- 主分类号： G06F9/38
- IPC分类号： G06F9/38
摘要：
The parallelism of a multi-pipelined digital computer is enhanced by detection of branch instructions from the execution pipelines and concurrent processing of up to two of the detected instructions in parallel with the operations of the execution pipelines. Certain branch instructions, when detected, are removed altogether from the pipeline, but still processed. The processing is synchronized with the execution pipeline to, first, predict an outcome for detected branch instructions, second, test the conditions for branch instructions at their proper place in the execution sequence to determine whether the predicted outcome was correct, and third, fetch a corrected target instruction if the prediction proves wrong.
公开/授权文献
- US5738177A Production assembly tool 公开/授权日：1998-04-14
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