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1.发明授权Pipeline for removing and concurrently executing two or more branch instructions in synchronization with other instructions executing in the execution unit 失效用于与在执行单元中执行的其他指令同步地去除并同时执行两个或更多个分支指令的流水线
公开(公告)号：US5287467A
公开(公告)日：1994-02-15
申请号：US687309
申请日：1991-04-18
IPC分类号： G06F9/38
CPC分类号： G06F9/3853 , G06F9/383 , G06F9/3832 , G06F9/3844 , G06F9/3885
摘要： The parallelism of a multi-pipelined digital computer is enhanced by detection of branch instructions from the execution pipelines and concurrent processing of up to two of the detected instructions in parallel with the operations of the execution pipelines. Certain branch instructions, when detected, are removed altogether from the pipeline, but still processed. The processing is synchronized with the execution pipeline to, first, predict an outcome for detected branch instructions, second, test the conditions for branch instructions at their proper place in the execution sequence to determine whether the predicted outcome was correct, and third, fetch a corrected target instruction if the prediction proves wrong.
摘要翻译： 多行数字计算机的并行性通过检测来自执行流水线的分支指令和最多两个检测到的指令与执行管线的操作并行处理来增强。 当检测到某些分支指令完全从管道中删除，但仍然被处理。 该处理与执行流水线同步，首先预测检测到的分支指令的结果，其次，在执行序列中的适当位置测试分支指令的条件，以确定预测结果是否正确，第三，获取 如果预测错误，则修正目标指令。
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2.发明授权System for executing scalar instructions in parallel based on control bits appended by compounding decoder 失效基于由复合解码器附加的控制位并行执行标量指令的系统
公开(公告)号：US5504932A
公开(公告)日：1996-04-02
申请号：US488464
申请日：1995-06-07
CPC分类号： G06F9/382 , G06F9/30149 , G06F9/3017 , G06F9/3808 , G06F9/3812 , G06F9/3853 , G06F9/3885
摘要： An instruction processor system for decoding compound instructions created from a series of base instructions of a scalar machine, the processor generating a series of compound instructions with an instruction format text having appended control bits in the instruction format text enabling the execution of the compound instruction format text in said instruction processor with a compounding facility which fetches and decodes compound instructions which can be executed as compounded and single instructions by the arithmetic and logic units of the instruction processor while preserving intact the scalar execution of the base instructions of a scalar machine which were originally in storage. The system nullifies any execution of a member instruction unit of a compound instruction upon occurrence of possible conditions, such as branch, which would affect the correctness of recording results of execution of the member instruction unit portion based upon the interrelationship of member units of the compound instruction with other instructions. The resultant series of compounded instructions generally executes in a faster manner than the original format which is preserved due to the parallel nature of the compounded instruction stream which is executed.
摘要翻译： 一种指令处理器系统，用于对由标量机的一系列基本指令产生的复合指令进行解码，该处理器产生具有指令格式文本的指令格式文本的一系列复合指令，该指令格式文本具有能够执行复合指令格式的指令格式文本中的附加控制位 所述指令处理器中的文本具有复合设备，该复合设备提取和解码可由指令处理器的算术和逻辑单元作为复合指令和单个指令执行的复合指令，同时完整地保持标量机的基本指令的标量执行， 最初在存储。 该系统在发生可能的条件（例如分支）时，使复合指令的成员指令单元的任何执行无效，这将基于化合物的成员单元的相互关系而影响成员指令单元部分执行的记录结果的正确性 指令与其他指令。 所得到的一系列复合指令通常比由被执行的复合指令流的并行特性而保留的原始格式更快地执行。
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3.发明授权System for issuing instructions for parallel execution subsequent to branch into a group of member instructions with compoundability in dictation tag 失效用于发出并行执行指令的系统，在分支到一组成员指令之后，具有口语标签中的复合性
公开(公告)号：US5303356A
公开(公告)日：1994-04-12
申请号：US677685
申请日：1991-03-29
CPC分类号： G06F9/3853 , G06F9/30152 , G06F9/3017 , G06F9/3802 , G06F9/3808 , G06F9/3812 , G06F9/382 , G06F9/3885
摘要： An instruction processor system for decoding compound instructions created from a series of base instructions of a scalar machine, the processor generating a series of compound instructions with an instruction format text having appended control bits in the instruction format text enabling the execution of the compound instruction format text in said instruction processor with a compounding facility which fetches and decodes compound instructions which can be executed as compounded and single instructions by the arithmetic and logic units of the instruction processor while preserving intact the scalar execution of the base instructions of a scalar machine which were originally in storage. The system nullifies any execution of a member instruction unit of a compound instruction upon occurrence of possible conditions, such as branch, which would affect the correctness of recording results of execution of the member instruction unit portion based upon the interrelationship of member units of the compound instruction with other instructions. The resultant series of compounded instructions generally executes in a faster manner than the original format which is preserved due to the parallel nature of the compounded instruction stream which is executed.
摘要翻译： 一种指令处理器系统，用于对由标量机的一系列基本指令产生的复合指令进行解码，该处理器产生具有指令格式文本的指令格式文本的一系列复合指令，该指令格式文本具有能够执行复合指令格式的指令格式文本中的附加控制位 所述指令处理器中的文本具有复合设备，该复合设备提取和解码可由指令处理器的算术和逻辑单元作为复合指令和单个指令执行的复合指令，同时完整地保持标量机的基本指令的标量执行， 最初在存储。 该系统在发生可能的条件（例如分支）时，使复合指令的成员指令单元的任何执行无效，这将基于化合物的成员单元的相互关系而影响成员指令单元部分执行的记录结果的正确性 指令与其他指令。 所得到的一系列复合指令通常比由被执行的复合指令流的并行特性而保留的原始格式更快地执行。
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4.发明授权
公开(公告)号：US5475853A
公开(公告)日：1995-12-12
申请号：US186225
申请日：1994-01-24
CPC分类号： G06F9/382 , G06F9/3802 , G06F9/3853
摘要： A digital computer system capable of processing two or more computer instructions in parallel and having a cache storage unit for temporarily storing machine-level computer instructions in their journey from a higher-level storage unit of the computer system to the functional units which process the instructions. The computer system includes an instruction compounding unit located intermediate to the higher-level storage unit and the cache storage unit for analyzing the instructions and adding to each instruction a tag field which indicates whether or not that instruction may be processed in parallel with one or more neighboring instructions in the instruction stream. These tagged instructions are then stored in the cache unit. The computer system further includes a plurality of functional instruction processing units which operate in parallel with one another. The instructions supplied to these functional units are obtained from the cache storage unit. At instruction issue time, the tag fields of the instructions are examined and those tagged for parallel processing are sent to different ones of the functional units in accordance with the codings of their operation code fields.
摘要翻译： 一种数字计算机系统，其能够并行处理两个或更多个计算机指令，并且具有高速缓存存储单元，用于在从计算机系统的更高级存储单元到处理指令的功能单元之间临时存储机器级计算机指令 。 计算机系统包括位于上级存储单元的中间的指令复合单元和高速缓存存储单元，用于分析指令，并且向每个指令添加指示该指令是否可以与一个或多个并行处理的标签字段 指令流中的相邻指令。 然后将这些标记的指令存储在高速缓存单元中。 计算机系统还包括彼此并行操作的多个功能指令处理单元。 提供给这些功能单元的指令从缓存存储单元获得。 在指令发布时，根据其操作代码字段的编码，检查指令的标签字段并将用于并行处理的标记字段发送到不同的功能单元。
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公开(公告)号：US5423011A
公开(公告)日：1995-06-06
申请号：US897214
申请日：1992-06-11
CPC分类号： G06F9/3844
摘要： Apparatus for retaining the branch prediction bits of a line displaced from an integrated cache/branch history table and using the retained bits to initialize the prediction bits should that line be brought back into the cache, the operation of which may be overlapped with the activities normally associated with displacing a cache line with one fetched from memory, thus imposing no instruction processing penalty. The apparatus consists of an associative memory that provides storage for branch prediction bits associated with cache lines and comparison means for matching stored prediction bits with their corresponding cache lines.
摘要翻译： 用于保留从集成高速缓存/分支历史表中移位的行的分支预测位并使用保留的比特来初始化预测比特的装置，该线将被带回到高速缓存中，其操作可以与正常的活动重叠 与从存储器中取出的一个缓存行移位相关联，因此不施加任何指令处理损失。 该装置包括相关存储器，其提供与高速缓存行相关联的分支预测位的存储和用于将存储的预测位与其对应的高速缓存行进行匹配的比较装置。
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6.发明授权Method for processing instructions for parallel execution including storing instruction sequences along with compounding information in cache 失效用于处理并行执行指令的方法，包括将指令序列与复合信息一起存储在高速缓存中
公开(公告)号：US6029240A
公开(公告)日：2000-02-22
申请号：US453948
申请日：1995-05-30
CPC分类号： G06F9/382 , G06F9/30152 , G06F9/3017 , G06F9/3808 , G06F9/3812 , G06F9/3842 , G06F9/3853 , G06F9/3885
摘要： A digital computer system capable of processing two or more computer instructions in parallel and having a cache storage unit for temporarily storing machine-level computer instructions in their journey from a higher-level storage unit of the computer system to the functional units which process the instructions. The computer system includes an instruction compounding unit located intermediate to the higher-level storage unit and the cache storage unit for analyzing the instructions and generating for to each instruction a compounding information which indicates whether or not that instruction may be processed in parallel with one or more neighboring instructions in the instruction stream. These tagged instructions are then stored in the cache unit with the compounding information. The computer system further includes a plurality of functional instruction processing units which operate in parallel with one another. The instructions supplied to these functional units are obtained from the cache storage unit. At instruction issue time, the compounding information for the instructions is examined and those instructions indicated for parallel processing are sent to different ones of the functional units in accordance with the codings of their operation code fields.
摘要翻译： 一种数字计算机系统，其能够并行处理两个或更多个计算机指令，并且具有高速缓存存储单元，用于在从计算机系统的更高级存储单元到处理指令的功能单元的旅程中临时存储机器级计算机指令 。 该计算机系统包括位于上级存储单元中间的指令复合单元和高速缓存存储单元，用于分析指令，并为每个指令生成指示该指令是否可以与一个或者另一个并行处理的复合信息 更多相邻指令在指令流中。 然后将这些标记的指令与复合信息一起存储在高速缓存单元中。 计算机系统还包括彼此并行操作的多个功能指令处理单元。 提供给这些功能单元的指令从缓存存储单元获得。 在指令发布时，检查指令的复合信息，并根据其操作码字段的编码将指示用于并行处理的指令发送到不同的功能单元。
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7.发明授权Apparatus and method for storing and initializing branch prediction with selective information transfer 失效用选择性信息传输存储和初始化分支预测的装置和方法
公开(公告)号：US5649178A
公开(公告)日：1997-07-15
申请号：US474017
申请日：1995-06-07
CPC分类号： G06F9/3806 , G06F9/3844
摘要： Apparatus for retaining the branch prediction bits of a line displaced from an integrated cache/branch history table and using the retained bits to initialize the prediction bits should that line be brought back into the cache, the operation of which may be overlapped with the activities normally associated with displacing a cache line with one fetched from memory, thus imposing no instruction processing penalty. The apparatus consists of an associative memory that provides storage for branch prediction bits associated with cache lines and comparison means for matching stored prediction bits with their corresponding cache lines.
摘要翻译： 用于保留从集成高速缓存/分支历史表中移位的行的分支预测位并使用保留的比特来初始化预测比特的装置，该线将被带回到高速缓存中，其操作可以与正常的活动重叠 与从存储器中取出的一个缓存行移位相关联，因此不施加任何指令处理损失。 该装置包括相关存储器，其提供与高速缓存行相关联的分支预测位的存储和用于将存储的预测位与其对应的高速缓存行进行匹配的比较装置。
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公开(公告)号：US5459844A
公开(公告)日：1995-10-17
申请号：US287435
申请日：1994-08-08
CPC分类号： G06F9/382 , G06F9/3853 , G06F9/3885
摘要： A digital computer system capable of processing two or more computer instructions in parallel and having a main memory unit for storing information blocks including the computer instructions includes an instruction compounding unit for analyzing the instructions and adding to each instruction a tag field which indicates whether or not that instruction may be processed in parallel with another neighboring instruction. Tagged instructions are stored in the main memory. The computer system further includes a plurality of functional instruction processing units which operate in parallel with one another. The instructions supplied to the functional units are obtained from the memory by way of a cache storage unit. At instruction issue time, the tag fields of the instructions are examined and those tagged for parallel processing are sent to different ones of the functional units in accordance with the codings of their operation code fields.
摘要翻译： 一种数字计算机系统，其能够并行处理两个或更多个计算机指令，并且具有用于存储包括计算机指令的信息块的主存储单元，包括用于分析指令的指令复合单元，并向每个指令添加指示是否指示的指示字段 该指令可以与另一个相邻指令并行处理。 标记的指令存储在主存储器中。 计算机系统还包括彼此并行操作的多个功能指令处理单元。 提供给功能单元的指令通过高速缓存存储单元从存储器获得。 在指令发布时，根据其操作代码字段的编码，检查指令的标签字段并将用于并行处理的标记字段发送到不同的功能单元。
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公开(公告)号：US5051940A
公开(公告)日：1991-09-24
申请号：US504910
申请日：1990-04-04
CPC分类号： G06F7/575 , G06F9/3001 , G06F9/3836 , G06F9/3853 , G06F9/3855
摘要： A multi-function ALU (arithmetic/logic unit) for use in digital data processing facilitates the execution of instructions in parallel, thereby enhancing processor performance. The proposed apparatus reduces the instruction execution latency that results from data dependency hazards in a pipelined machine. This latency reduction is accomplished by collapsing the interlocks due to these hazards. The proposed apparatus achieves performance improvement while maintaining compatibility with previous implementations designed using an identical architecture.
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公开(公告)号：USRE35311E
公开(公告)日：1996-08-06
申请号：US292606
申请日：1994-08-18
CPC分类号： G06F9/3853 , G06F7/575 , G06F9/3001 , B01F2003/0896 , G06F7/4991
摘要： A multi-function ALU (arithmetic/logic unit) for use in digital data processing facilitates the execution of instructions in parallel, thereby enhancing processor performance. The proposed apparatus reduces the instruction execution latency that results from data dependency hazards in a pipelined machine. This latency reduction is accomplished by collapsing the interlocks due to these hazards. The proposed apparatus achieves performance improvement while maintaining compatibility with previous implementations designed using an identical architecture.
摘要翻译： 用于数字数据处理的多功能ALU（算术/逻辑单元）有助于并行执行指令，从而提高处理器的性能。 所提出的装置减少了由流水线机器中的数据依赖性危害引起的指令执行延迟。 这种延迟减少是由于这些危害而使互锁崩溃而实现的。 所提出的装置实现性能改进，同时保持与使用相同架构设计的先前实现的兼容性。
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