发明授权
- 专利标题: High speed logic circuit
- 专利标题(中): 高速逻辑电路
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申请号: US942181申请日: 1992-09-09
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公开(公告)号: US5293084A公开(公告)日: 1994-03-08
- 发明人: Hiroyuki Itoh , Toshiyuki Usagawa , Atsushi Takai
- 申请人: Hiroyuki Itoh , Toshiyuki Usagawa , Atsushi Takai
- 申请人地址: JPX Tokyo
- 专利权人: Hitachi, Ltd.
- 当前专利权人: Hitachi, Ltd.
- 当前专利权人地址: JPX Tokyo
- 优先权: JPX3-230043 19910910
- 主分类号: H01L21/8249
- IPC分类号: H01L21/8249 ; H01L27/06 ; H01L29/737 ; H03K17/567 ; H03K19/094 ; H03K19/08 ; H01L29/161
摘要:
In a high speed logic circuit using a vertical hetero-junction bipolar transistor, in which two-dimensional carriers formed at a semiconductor hetero-junction interface are used as a base layer, the uppermost layer being a collector layer, the lowest layer being an emitter layer, two base electrodes making contact with the base layer are disposed so as to put a collector electrode, which is electrically in contact with the collector layer, therebetween. The base electrodes are used at the same time as a source electrode and a drain electrode, respectively, of a field effect transistor using the two-dimensional carriers as an active layer. The high speed logic circuit is so constructed that one of the base electrodes of the bipolar transistor is an input terminal; the other is connected with a power supply; the emitter is grounded; and the collector is an output terminal.
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