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    Mixed signal device with different pluralities of digital cells
    1.
    发明授权
    Mixed signal device with different pluralities of digital cells 有权

    公开(公告)号：US12021526B2

    公开(公告)日：2024-06-25

    申请号：US17684098

    申请日：2022-03-01

    Applicant: Sandeep Kumar Gupta

    Inventor： Sandeep Kumar Gupta

    IPC: H03K19/08 ,  H03K19/0185 ,  H03K19/17784 ,  H03K19/20

    CPC classification number: H03K19/0813 ,  H03K19/018585 ,  H03K19/17784 ,  H03K19/20

    Abstract: Apparatuses, and methods, for digital cells power reduction are disclosed. For an embodiment, a first plurality of digital logic cells are directly connected to a Vdd terminal and a Vss terminal that have a potential difference of VDD, a second plurality of digital logic cells being directly connected to a Vdd_R terminal and a Vss_R terminal, wherein a potential difference between the Vdd_R terminal and the Vss terminal is (VDD−X1), and a potential difference between the Vss_R terminal and the Vss terminal is X2, wherein at least one digital logic cell has at least one of (a) an input connected to an output of at least one digital logic cell of the second plurality, or (b) an output connected to an input of at least one digital logic cell of the second plurality. Vdd, Vdd_R and Vss_R terminal voltages can be generated by an array of devices.

    LOGIC GATE DEVICE
    4.
    发明公开
    LOGIC GATE DEVICE 审中-公开

    公开(公告)号：US20240063296A1

    公开(公告)日：2024-02-22

    申请号：US18220868

    申请日：2023-07-12

    Applicant: Tsinghua University ,  HON HAI PRECISION INDUSTRY CO., LTD.

    Inventor： GUANG-QI ZHANG ,  YANG WEI ,  SHOU-SHAN FAN

    IPC: H01L29/68 ,  H03K19/08 ,  H01L29/24 ,  H01L29/76

    CPC classification number: H01L29/685 ,  H03K19/08 ,  H01L29/24 ,  H01L29/7606

    Abstract: The present application provides a logic gate device. The logic gate device includes a gate electrode, a gate insulating layer, a bottom electrode, a two-dimensional semiconductor layer, a first top electrode and a second electrode. The gate insulating layer is located on the gate electrode. The bottom electrode is located on the gate insulating layer. The two-dimensional semiconductor layer is located on the bottom electrode and simultaneously covers the gate insulating layer. The first top electrode and the second electrode are located on the two-dimensional semiconductor layer. The bottom electrode, the two-dimensional semiconductor layer and the gate insulating layer form an air gap, and the air gap is distributed at both sides of the bottom electrode. The gate electrode is configured to connect a gate voltage, and the first top electrode and the second top electrode are configured to connect a signal input terminal.

    Logic circuit and semiconductor device formed using unipolar transistor
    5.
    发明授权
    Logic circuit and semiconductor device formed using unipolar transistor 有权

    公开(公告)号：US11777502B2

    公开(公告)日：2023-10-03

    申请号：US17441804

    申请日：2020-03-12

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Hiroki Inoue ,  Munehiro Kozuma ,  Takeshi Aoki ,  Shuji Fukai ,  Fumika Akasawa ,  Sho Nagao

    IPC: H03K19/08 ,  H03K17/56 ,  H01L27/12 ,  H01L27/13

    CPC classification number: H03K19/08 ,  H03K17/56 ,  H01L27/1207 ,  H01L27/13

    Abstract: A semiconductor device is provided; the semiconductor device includes unipolar transistors. A steady-state current does not flow in the semiconductor device. The semiconductor device uses a high-level potential and a low-level potential to express a high level and a low level, respectively. The semiconductor device includes unipolar transistors, a capacitor, first and second input terminals, and an output terminal. To the second input terminal, a signal is input whose logic is inverted from the logic of a signal input to the first input terminal. The semiconductor device has a circuit structure called bootstrap in which two unipolar transistors are connected in series between the high-level potential and the low-level potential and a capacitor is provided between an output terminal and a gate of one of the two transistors. A delay is caused between the gate of the transistor and the signal output from the output terminal, whereby the bootstrap can be certainly performed.

    Controller area network transceiver
    8.
    发明授权
    Controller area network transceiver 有权

    公开(公告)号：US11588663B1

    公开(公告)日：2023-02-21

    申请号：US17450191

    申请日：2021-10-07

    Applicant: NXP B.V.

    Inventor： Matthias Berthold Muth ,  Clemens Gerhardus Johannes de Haas ,  Axel Engelhard

    IPC: H04L12/40 ,  H03K19/08 ,  G06F13/374

    Abstract: A Controller Area Network (CAN) transceiver determines a voltage differential signal from analog signaling and provides a digital output signal at a receiver output to a CAN controller based on the voltage differential signal. The analog signaling received from the CAN bus can operate with a first voltage level scheme of a first CAN protocol and a second voltage level scheme for a second CAN protocol. A first comparator compares the voltage differential signal to a first threshold which is set to a value which differentiates between a logic low bit and logic high bit in accordance with the second CAN protocol. Filtering circuitry selectively filters an output of the first comparator based on detection of noise on the CAN bus to provide a first digital signal indicative of activity on the CAN bus according to the second CAN protocol.

    Potential generating circuit, inverter, delay circuit, and logic gate circuit
    9.
    发明授权
    Potential generating circuit, inverter, delay circuit, and logic gate circuit 有权

    公开(公告)号：US11550350B2

    公开(公告)日：2023-01-10

    申请号：US17404149

    申请日：2021-08-17

    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

    Inventor： Lei Zhu ,  Zhiyong Chen ,  Jinlai Luo

    IPC: G05F1/575 ,  H03K19/08 ,  H03K5/01 ,  H03K5/00

    Abstract: A potential generating circuit includes a first transistor and a second transistor. Potential at a substrate of the first transistor varies with a first parameter. The first parameter is any one of a supply voltage, an operating temperature, as well as a manufacturing process of the potential generating circuit. Potential at a substrate of the second transistor varies with the first parameter. A gate of the first transistor is connected to a drain of the first transistor. The substrate of the first transistor serves as a first output of the potential generating circuit. A gate of the second transistor is connected to a drain of the second transistor. The substrate of the second transistor serves as a second output of the potential generating circuit.

    Clock step control circuit and method thereof
    10.
    发明授权
    Clock step control circuit and method thereof 有权

    公开(公告)号：US11381245B1

    公开(公告)日：2022-07-05

    申请号：US17468686

    申请日：2021-09-08

    Applicant: Shanghai Biren Technology Co., Ltd

    Inventor： Zheng Tian ,  YiKai Liang ,  Linglan Zhang ,  WenQi Li ,  DongCai Li ,  TingTing Yu

    IPC: H03K23/60 ,  H03K23/00 ,  H03K19/08 ,  H03K19/173 ,  H03K21/10

    Abstract: The disclosure provides a clock step control circuit and a method thereof. The clock step control circuit includes a clock divider, a multiplexer, and a controller. The clock divider receives a first clock signal and outputs multiple second clock signals. The multiplexer receives the second clock signals and outputs one of the second clock signals. The controller is coupled to the clock divider and the multiplexer. When the controller receives an interrupt signal, the controller outputs a selection signal to the multiplexer according to the interrupt signal. The multiplexer outputs another one of the second clock signals according to the selection signal. The clock step control circuit and the method thereof in the disclosure can appropriately switch the clock signal to output a clock signal with an appropriate clock frequency.

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