发明授权
- 专利标题： Method and apparatus for interruption processing in multi-processor system
- 专利标题（中）： 多处理器系统中的中断处理方法和装置
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申请号： US408731申请日： 1989-09-18
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公开(公告)号： US5297290A公开(公告)日： 1994-03-22
- 发明人: Koji Masui , Masayuki Tanji
- 申请人： Koji Masui , Masayuki Tanji
- 申请人地址： JPX Tokyo
- 专利权人： Hitachi, Ltd.
- 当前专利权人： Hitachi, Ltd.
- 当前专利权人地址： JPX Tokyo
- 优先权： JPX63-233426 19880920
- 主分类号： G06F15/16
- IPC分类号： G06F15/16 ; G06F9/46 ; G06F13/24 ; G06F15/177 ; G06F13/14 ; G06F13/368
摘要：
An interruption signal from a common input/output device is coupled to all processors through a common bus, and each processor issues to the common bus its own interruption receipt acceptance or negation state and the respective processors watch and decide individually interruption receipt acceptance or negation states on the common bus of the individual processors. Only one of processors which are ready to accept the receipt of interruption is allowed to accept the receipt of an interruption signal from the common input/output device in accordance with a predetermined priority.
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