发明授权
- 专利标题： Error correction system including a plurality of processor elements which are capable of performing several kinds of processing for error correction in parallel
- 专利标题（中）： 错误校正系统包括能够并行执行错误纠正的多种处理的多个处理器元件
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申请号： US711990申请日： 1991-06-07
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公开(公告)号： US5315600A公开(公告)日： 1994-05-24
- 发明人: Keiichi Iwamura , Takayuki Aizawa , Izumi Narita , Takatoshi Suzuki
- 申请人： Keiichi Iwamura , Takayuki Aizawa , Izumi Narita , Takatoshi Suzuki
- 申请人地址： JPX Tokyo
- 专利权人： Canon Kabushiki Kaisha
- 当前专利权人： Canon Kabushiki Kaisha
- 当前专利权人地址： JPX Tokyo
- 优先权： JPX2-168331 19900628
- 主分类号： H03M13/00
- IPC分类号： H03M13/00 ; G06F11/10 ; H03M13/15 ; G06F11/00
摘要：
Respective processes of decoding in error correction are subjected to parallel processing using a plurality of processing elements (PEs) each having the same configuration. At any given time, when processing of one process has been terminated, processing proceeds to a PE having the highest priority among PEs waiting for processing. The PE which has received data recognizes and executes the next process for that data.
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