A clock mechanism in modules connected to a bus over which asynchronous operations are performed wherein clock pulses are generated that can clock the transmission or capture of data and the transitioning of acknowledge or synchronization lines. Each clock mechanism generates its clock pulses based on the receipt of signals associated with synchronization or acknowledge bus lines. The clock mechanism includes a multiplexer which provides to a resettable latch a signal associated with the condition of the selected line. The resettable latch, in conjunction with a delay element produces the clock pulses.