发明授权
US5323065A Semiconductor integrated circuit device having edge trigger flip-flop
circuit for decreasing delay time
失效
具有用于减少延迟时间的边缘触发触发电路的半导体集成电路器件
- 专利标题： Semiconductor integrated circuit device having edge trigger flip-flop circuit for decreasing delay time
- 专利标题（中）： 具有用于减少延迟时间的边缘触发触发电路的半导体集成电路器件
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申请号： US924941申请日： 1992-08-05
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公开(公告)号： US5323065A公开(公告)日： 1994-06-21
- 发明人: Kou Ebihara , Kunihiko Kawaguchi
- 申请人： Kou Ebihara , Kunihiko Kawaguchi
- 申请人地址： JPX Kawasaki
- 专利权人： Fujitsu Limited
- 当前专利权人： Fujitsu Limited
- 当前专利权人地址： JPX Kawasaki
- 优先权： JPX3-199458 19910808
- 主分类号： H03K3/012
- IPC分类号： H03K3/012 ; H03K3/037 ; H03K3/289 ; H03K5/12
摘要：
A semiconductor integrated circuit device includes a preceding circuit portion, a flip-flop circuit portion receiving complementary output signals of the preceding circuit portion, for latching data in accordance with the complementary output signals of the preceding circuit portion, and a compensation circuit portion receiving complementary output signals of the flip-flop circuit portion and receiving the complementary output signals of the preceding circuit portion without passing through the flip-flop circuit portion, for compensating driving power and decreasing a delay time of a specific phase. Therefore, the delay time of the semiconductor integrated circuit device can be decreased in one phase (specific phase).
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