发明授权
- 专利标题： Dielectrically isolated high and low voltage substrate regions
- 专利标题（中）： 绝缘隔离的高低压基板区域
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申请号： US850964申请日： 1992-03-11
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公开(公告)号： US5332920A公开(公告)日： 1994-07-26
- 发明人: Akio Nakagawa , Kazuyoshi Furukawa , Tsuneo Ogura , Katsujiro Tanzawa
- 申请人： Akio Nakagawa , Kazuyoshi Furukawa , Tsuneo Ogura , Katsujiro Tanzawa
- 申请人地址： JPX Kawasaki
- 专利权人： Kabushiki Kaisha Toshiba
- 当前专利权人： Kabushiki Kaisha Toshiba
- 当前专利权人地址： JPX Kawasaki
- 优先权： JPX63-26787 19880208; JPX63-246441 19880930; JPX1-122311 19890516; JPX1-202936 19890807; JPX1-318980 19891211
- 主分类号： H01L21/761
- IPC分类号： H01L21/761 ; H01L21/762 ; H01L21/763 ; H01L27/088 ; H01L27/12 ; H01L29/739 ; H01L29/70
摘要：
A dielectric isolation substrate comprises a first semiconductor wafer, a second semiconductor wafer bonded on the first semiconductor wafer with a first insulating layer interposed therebetween, a semiconductor layer formed on the second semiconductor wafer, a first groove formed in the semiconductor layer and the second semiconductor wafer so as to reach the first insulating layer, thereby isolating the semiconductor layer and the second semiconductor wafer, and a second insulating layer formed on the side face of the first groove or embedded in the first groove. In this dielectric isolation substrate, a high breakdown voltage element and a low breakdown voltage element are formed in a region isolated by the first groove.
公开/授权文献
- US5836077A Method for forming grooves 公开/授权日：1998-11-17
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