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US5341092A Testability architecture and techniques for programmable interconnect architecture 失效
可测试架构和可编程互连架构技术

Testability architecture and techniques for programmable interconnect architecture
摘要：
In an integrated circuit including a first conductor disposed in a first direction, a plurality of second conductors forming intersections with the first conductor, and a plurality of antifuses connected between the first conductor and the second conductors at the intersections, a method for testing the integrity of the plurality of antifuses after attempting to program a selected one of the antifuses, including the steps of precharging each of the second conductors to a first preselected voltage potential such that a selected dynamic voltage is placed on each of the second conductors; placing a second voltage potential on the first conductor, wherein the difference between the first voltage potential and the second voltage potential is less than the voltage necessary to cause degradation of a good antifuse; waiting a preselected time; and sensing the voltage potential on each of the second conductors.
摘要（中）：

在包括沿第一方向设置的第一导体的集成电路中，形成与第一导体相交的多个第二导体以及在交叉点处连接在第一导体与第二导体之间的多个反熔丝，用于测试完整性的方法 在尝试编程所选择的一个反熔丝之后的多个反熔丝中，包括以下步骤：将每个第二导体预充电到第一预选电压电位，使得所选择的动态电压放置在每个第二导体上; 在所述第一导体上放置第二电压电位，其中所述第一电压电位和所述第二电压电位之间的差小于引起良好反熔丝劣化所需的电压; 等待预选时间; 并感测每个第二导体上的电压电位。

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