发明授权
US5365463A Method for evaluating the timing of digital machines with statistical
variability in their delays
失效
用于评估其延迟的统计变异性的数字机器的时序的方法
- 专利标题: Method for evaluating the timing of digital machines with statistical variability in their delays
- 专利标题(中): 用于评估其延迟的统计变异性的数字机器的时序的方法
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申请号: US631827申请日: 1990-12-21
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公开(公告)号: US5365463A公开(公告)日: 1994-11-15
- 发明人: Wilm E. Donath , Robert B. Hitchcock , Jeffrey P. Soreff
- 申请人: Wilm E. Donath , Robert B. Hitchcock , Jeffrey P. Soreff
- 申请人地址: NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: NY Armonk
- 主分类号: G01R31/28
- IPC分类号: G01R31/28 ; G06F11/34 ; G06F17/50 ; G06F19/00 ; G06Q50/00 ; G06F15/60
摘要:
An apparatus and method for simulating timing performance of designs of digital machines which allows for the avoidance of lumping of correlation of correlation coefficients which may be significant to the slacks which may occur in a particular design. Delays of particular digital elements are derived by random selections from distributions of delay values based on correlations between different observed or otherwise reasonable distributions of relative delays of digital element pairs including pairs of senses of logic value transitions, pairs of technologies and pairs of packaging levels as an accuracy enhancement. Delay distributions are built up of weighted sums of other distributions and may be asymmetrical. Several computational enhancements disclosed include arrangements allowing reductions in paging (e.g. reduction in number of accesses to secondary memory). Other enhancements include application enhancements by providing generality of methodology and accommodation of large model size, further computational enhancement by providing generality of delay propagation algorithms and diagnostic enhancements by providing cycle time/yield data and allowance of re-simulation of failure modes of design performance by retaining seed values corresponding to simulated machines.
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