A digital signal transmission system having monitor equipment including a serial/parallel (S/P) converter and a parallel/serial (P/S) converter both. The S/P converter is checked by the aid of a first monitor signal generating circuit that parallel distributes a pass pattern signal given at the input side of the S/P converter to respective individual channel lines for achieving a pass pattern check. The P/S converter is checked with the aid of a second monitor signal generating circuit that receives respective pass pattern signals given, at the input side of the P/S converter, to a multiplexed channel line sequentially at every frame to achieve a pass pattern check.