发明授权
US5371865A Computer with main memory and cache memory for employing array data
pre-load operation utilizing base-address and offset operand
失效
具有主存储器和高速缓冲存储器的计算机，用于使用基地址和偏移操作数的阵列数据预加载操作
- 专利标题： Computer with main memory and cache memory for employing array data pre-load operation utilizing base-address and offset operand
- 专利标题（中）： 具有主存储器和高速缓冲存储器的计算机，用于使用基地址和偏移操作数的阵列数据预加载操作
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申请号： US715932申请日： 1991-06-14
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公开(公告)号： US5371865A公开(公告)日： 1994-12-06
- 发明人: Takeshi Aikawa , Kenji Minagawa , Mitsuo Saito
- 申请人： Takeshi Aikawa , Kenji Minagawa , Mitsuo Saito
- 申请人地址： JPX Tokyo
- 专利权人： Kabushiki Kaisha Toshiba
- 当前专利权人： Kabushiki Kaisha Toshiba
- 当前专利权人地址： JPX Tokyo
- 优先权： JPX2-155776 19900614
- 主分类号： G06F9/38
- IPC分类号： G06F9/38 ; G06F12/08 ; G06F12/12 ; G06F12/02
摘要：
A computer having a main memory for storing a plurality of data, a cache memory for temporarily storing a portion of the plurality of data, a processor for accessing data stored in the cache memory and processing the data according to instructions. The processor has an access instruction combined with a preload instruction, and an access instruction only for accessing data, and includes indicator circuitry for indicating a preload condition to the cache memory when the processor accesses data from the cache memory according to the access instruction combined with the preload instruction. The cache memory preloads data to be accessed next by the processor from the main memory when the processor indicates the preload condition.
公开/授权文献
- US5962901A Semiconductor configuration for an insulating transistor 公开/授权日：1999-10-05
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