An acceleration and deceleration controlling apparatus in which a positional moving amount supplied from a host is converted into an accumulated value of absolute positions by two serially connected accumulators to be output to a first stage of a buffer registers 4. A switch 5 is provided to read out a value from a desired register among the buffer registers 4. The switch 5 changes the substantial number of stages of the buffer registers 4. At the same time, by correspondingly switching the divisor of the divider 7, the time constant for the acceleration and deceleration are desirably changed, which contributes to optimize the acceleration and deceleration time and to reduce the processing time.