In a disclosed PLL circuit, a constant voltage output by a constant voltage power supply 6 for obtaining a signal with a frequency equivalent to that obtained in a synchronized state is added to a signal output by a filter 3 by means of an adder 7. A signal output by the adder 7 representing the sum of the voltage output by the constant-voltage power supply and the signal output by the filter is supplied to a voltage-controlled oscillator 4. With a reference signal Pi supplied, the PLL circuit functions like an ordinary PLL circuit. When the signal Pi becomes unavailable, however, a signal output by a reference-signal-input detecting circuit 5 for monitoring the reference signal Pi puts integrating components employed by the filter 3 in a short-circuit state, initializing information accumulated in the integrating components. In addition, the output of the filter is set to zero. In this state, only the constant voltage output by the constant-voltage power supply 6 is therefore supplied to the voltage-controlled oscillator 4.