发明授权
US5416918A Low skew system for interfacing asics by routing internal clock off-chip
to external delay element then feeding back to on-chip drivers
失效
低偏移系统，用于通过将外部时钟片外到外部延迟元件，然后反馈到片上驱动器进行接口连接
- 专利标题： Low skew system for interfacing asics by routing internal clock off-chip to external delay element then feeding back to on-chip drivers
- 专利标题（中）： 低偏移系统，用于通过将外部时钟片外到外部延迟元件，然后反馈到片上驱动器进行接口连接
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申请号： US187264申请日： 1994-01-27
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公开(公告)号： US5416918A公开(公告)日： 1995-05-16
- 发明人: Craig A. Gleason , Robert J. Horning
- 申请人： Craig A. Gleason , Robert J. Horning
- 申请人地址： CA Palo Alto
- 专利权人： Hewlett-Packard Company
- 当前专利权人： Hewlett-Packard Company
- 当前专利权人地址： CA Palo Alto
- 主分类号： G06F1/10
- IPC分类号： G06F1/10 ; G06F1/04
摘要：
A low skew interface system for enabling an ASIC chip's receivers to latch information from one or more buses. The interface comprises a driver circuit connected to an internal clock of the chip for generating another clock signal with phase different from the phase of the internal clock. A delay element is located off the chip and connected to the driver circuit for delaying the clock signal, thereby generating a latch clock signal. The latch clock signal is sent back on-chip to enable the receivers to transfer information from one of the buses to the chip.
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