公开(公告)号：US5416918A

公开(公告)日：1995-05-16

申请号：US187264

申请日：1994-01-27

申请人： Craig A. Gleason ,  Robert J. Horning

发明人： Craig A. Gleason ,  Robert J. Horning

IPC分类号： G06F1/10 ,  G06F1/04

CPC分类号： G06F1/10

摘要： A low skew interface system for enabling an ASIC chip's receivers to latch information from one or more buses. The interface comprises a driver circuit connected to an internal clock of the chip for generating another clock signal with phase different from the phase of the internal clock. A delay element is located off the chip and connected to the driver circuit for delaying the clock signal, thereby generating a latch clock signal. The latch clock signal is sent back on-chip to enable the receivers to transfer information from one of the buses to the chip.

摘要翻译： 低偏移接口系统，用于使ASIC芯片的接收器能够锁存来自一个或多个总线的信息。 该接口包括连接到芯片的内部时钟的驱动器电路，用于产生具有不同于内部时钟的相位的相位的另一个时钟信号。 延迟元件位于芯片外并连接到驱动器电路，用于延迟时钟信号，从而产生锁存时钟信号。 锁存时钟信号在芯片上被送回，以使接收器能够将信息从一个总线传送到芯片。

公开(公告)号：US5263173A

公开(公告)日：1993-11-16

申请号：US727690

申请日：1991-07-10

申请人： Craig A. Gleason

发明人： Craig A. Gleason

IPC分类号： G06F1/04 ,  G11C7/10 ,  G11C7/22

CPC分类号： G11C7/1057 ,  G06F1/04 ,  G11C7/1051 ,  G11C7/22

摘要： An output driver and method including an output pad, for performing write operations from a central processor unit to a cache memory. The driver includes a pull-up circuit electrically connected to the output pad for switching the pad to a first logic state and a pull-down circuit electrically connected to the output pad for switching it to a second logic state. A plurality of signals are input to the pull-up and pull-down circuits to perform the switching of the output pad at integer and integer and a half clock cycles.

摘要翻译： 一种输出驱动器和方法，包括用于执行从中央处理器单元到高速缓冲存储器的写入操作的输出焊盘。 驱动器包括电连接到输出焊盘以将焊盘切换到第一逻辑状态的上拉电路和电连接到输出焊盘以将其切换到第二逻辑状态的下拉电路。 多个信号被输入到上拉和下拉电路，以整数和整数半个周期执行输出焊盘的切换。

公开(公告)号：US5337415A

公开(公告)日：1994-08-09

申请号：US984770

申请日：1992-12-04

申请人： Eric R. DeLano ,  Craig A. Gleason ,  Mark A. Forsyth

发明人： Eric R. DeLano ,  Craig A. Gleason ,  Mark A. Forsyth

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/382 ,  G06F9/3802 ,  G06F9/3822 ,  G06F9/3853

摘要： A system and method of producing predecode bits from instructions as instructions are copied from a memory system to a cache memory unit. A predecode unit, coupled between the memory unit and the cache memory unit, produces the predecode bits for utilization by a superscalar processor. The circuitry of the predecode unit is comprised of logic and latches. The predecode unit includes two main paths for transporting instruction information: a predecode path and an instruction path. The instruction path buffers instructions sent from memory to cache as information from these instructions are decoded in the predecode path. The predecode path includes a decoder and a bit information unit. The decoder identifies the instruction type by monitoring the op-code of instructions entering the predecode unit. The bit information unit is coupled to the decoder and receives signals indicating instruction type and passes these signals through logic gates to obtain whether instructions can be bundled. The bit information unit then transfers to cache bundle signals and instruction type signals. These signals are stored as predecode bits along with instructions from the instruction path in the cache.

摘要翻译： 从指令产生预解码位的系统和方法从存储器系统复制到高速缓冲存储器单元。 耦合在存储器单元和高速缓冲存储器单元之间的预解码单元产生用于由超标量处理器利用的预解码位。 预解码单元的电路由逻辑和锁存器组成。 预解码单元包括用于传送指令信息的两个主要路径：预解码路径和指令路径。 指令路径缓冲从存储器发送到高速缓存的指令，作为来自这些指令的信息在预解码路径中被解码。 预解码路径包括解码器和比特信息单元。 解码器通过监视进入预解码单元的指令的操作代码来识别指令类型。 比特信息单元耦合到解码器并接收指示指令类型的信号，并将这些信号通过逻辑门，以获得是否可以捆绑指令。 位信息单元然后传送到高速缓存包信号和指令类型信号。 这些信号作为预解码位与来自缓存中的指令路径的指令一起存储。

公开(公告)号：US5860096A

公开(公告)日：1999-01-12

申请号：US768417

申请日：1996-12-18

申请人： Stephen R. Undy ,  Patrick Knebel ,  Craig A. Gleason

发明人： Stephen R. Undy ,  Patrick Knebel ,  Craig A. Gleason

IPC分类号： G06F9/38 ,  G06F12/08

CPC分类号： G06F9/3814 ,  G06F12/0897 ,  G06F9/3802

摘要： A multi-level instruction cache memory system for a computer processor. A relatively large cache has both instructions and data. The large cache is the primary source of data for the processor. A smaller cache dedicated to instructions is also provided. The smaller cache is the primary source of instructions for the processor. Instructions are copied from the larger cache to the smaller cache during times when the processor is not accessing data in the larger cache. A prefetch buffer transfers instructions from the larger cache to the smaller cache. If a cache miss occurs for the smaller cache, and the instruction is in the prefetch buffer, the system provides the instruction with no delay relative to a fetch from the smaller instruction cache. If a cache miss occurs for the smaller cache, and the instruction is being fetched from the larger cache, or available in the larger cache, the system provides the instruction with minimal delay relative to a fetch from the smaller instruction cache.

摘要翻译： 一种用于计算机处理器的多级指令高速缓冲存储器系统。 相对较大的缓存具有指令和数据。 大型缓存是处理器的主要数据源。 还提供了一个专用于指令的较小缓存。 较小的缓存是处理器的主要指令源。 在处理器未访问较大缓存中的数据的时间期间，指令将从更大的缓存复制到较小的缓存。 预取缓冲区将指令从较大的缓存传输到较小的缓存。 如果较小的缓存出现高速缓存未命中，并且该指令位于预取缓冲区中，则该系统相对于从较小的指令高速缓存提取的指令没有延迟。 如果较小的缓存出现高速缓存未命中，并且指令正在从较大的缓存中取出，或者在较大的缓存中可用，则该系统相对于从较小的指令高速缓存取出的延迟最小化。

公开(公告)号：US5426771A

公开(公告)日：1995-06-20

申请号：US913571

申请日：1992-07-14

申请人： Thomas A. Asprey ,  Craig A. Gleason

发明人： Thomas A. Asprey ,  Craig A. Gleason

IPC分类号： G06F12/08

CPC分类号： G06F12/0893

摘要： A system and method for improving cache memory write cycle timing in a microprocessor system, having static random access memory (SRAM) cache memory, using two out-of-phase clock signals and delayed variants thereof. The present invention includes the steps of sending a write address to the cache memory at a positive transition of the first out-of-phase clock signal that marks the beginning of the write cycle; causing a write control signal to be asserted at a time marked by next occurring positive transition of the second out-of-phase clock signal; sending the data to be written to the SRAM at a time marked by a drive clock signal; and ending the write cycle at a time marked by a end-write clock. The drive clock signal is provided by delaying the first out-of-phase clock signal. The amount of delay introduced in providing the drive clock signal is selected to allow the SRAM sufficient time to tri-state its drivers after receiving the write-control signal. The end write signal is provided by delaying the second out-of-phase clock signal. The amount of delay introduced in providing the end-write clock is selected to allow the SRAM sufficient time to read data to be written off of the data bus. The delay is introduced into the clock signals using printed circuit trace delay lines. The length of the printed circuit trace delay lines is selected such that the drive clock and end-write clock transitions occur at the optimum time.

摘要翻译： 一种用于在微处理器系统中改进高速缓冲存储器写周期定时的系统和方法，具有使用两个异相时钟信号及其延迟变型的静态随机存取存储器（SRAM）高速缓冲存储器。 本发明包括以下步骤：以标志写入周期开始的第一异相时钟信号的正转变向高速缓存存储器发送写地址; 使得写入控制信号在由所述第二异相时钟信号的下一次正向跃迁标记的时间被断言; 在由驱动时钟信号标记的时间发送要写入SRAM的数据; 并在结束写入时钟标记的时间结束写周期。 通过延迟第一异相时钟信号来提供驱动时钟信号。 选择在提供驱动时钟信号时引入的延迟量，以允许SRAM在接收到写入控制信号之后足够的时间对其驱动器进行三态化。 通过延迟第二异相时钟信号来提供结束写入信号。 选择提供端写时钟引入的延迟量，以使SRAM有足够的时间来读取数据总线上的数据。 使用印刷电路跟踪延迟线将延迟引入时钟信号。 选择印刷电路迹线延迟线的长度，使得驱动时钟和结束写入时钟转换在最佳时间发生。