A nonvolatile memory (20) includes an array of floating gate transistors (22) organized as rows and columns. Word lines of adjacent rows are coupled together to form shared word lines. In one embodiment, a coupling transistor (56-61) is used to couple the sources of the floating gate transistors (36, 39-55) of a row to a predetermined potential in response to the shared word line being selected. The sources of the unselected floating gate transistors of the array (22) are isolated. In another embodiment, an inverter (113, 114, and 115) couples the sources to zero volts in response to the shared word line being selected. The conductivity of the floating gate transistors (36, 39-55) is controlled in response to the logic state of the shared word lines to ensure that unselected cells do not adversely affect the operation of the nonvolatile memory.