Invention Grant
US5426320A Integrated structure protection device for protecting logic-level power
MOS devices against electro-static discharges
失效
集成结构保护装置，用于保护逻辑级功率MOS器件免受静电放电
- Patent Title: Integrated structure protection device for protecting logic-level power MOS devices against electro-static discharges
- Patent Title (中): 集成结构保护装置，用于保护逻辑级功率MOS器件免受静电放电
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Application No.: US225147Application Date: 1994-04-08
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Publication No.: US5426320APublication Date: 1995-06-20
- Inventor: Raffaele Zambrano
- Applicant: Raffaele Zambrano
- Applicant Address: ITX Catania
- Assignee: Consorzio per la Ricera Sulla MMicroelectronica nel Mezzogiorno
- Current Assignee: Consorzio per la Ricera Sulla MMicroelectronica nel Mezzogiorno
- Current Assignee Address: ITX Catania
- Priority: EPX93830169 19930421
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L27/02 ; H01L27/04 ; H01L29/06 ; H01L29/10
Abstract:
An integrated structure protection device suitable for protecting a power MOS device from electrostatic discharges comprises a junction diode comprising a first electrode made of a highly doped region of a first conductivity type surrounded by a body region of a second conductivity type and representing a second electrode of the junction diode, which in turn is surrounded by a highly doped deep body region of said second conductivity type. The highly doped region is connected to a polysilicon gate layer representing the gate of the power MOS device, while the deep body region is connected to a source region of the power MOS.
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