公开(公告)号：US06872996B2

公开(公告)日：2005-03-29

申请号：US10621262

申请日：2003-07-15

Applicant: Nicolas Demange ,  Raffaele Zambrano

Inventor： Nicolas Demange ,  Raffaele Zambrano

IPC: H01L21/8242 ,  H01L21/8246 ,  H01L27/108 ,  H01L27/115 ,  H01G7/06

CPC classification number: H01L27/11502 ,  H01L27/10811 ,  H01L27/10888 ,  H01L27/115 ,  H01L27/11507

Abstract: The cells of the stacked type each comprise a MOS transistor formed in an active region of a substrate of semiconductor material and a capacitor formed above the active region; each MOS transistor has a first and a second conductive region and a control electrode and each capacitor has a first and a second plate separated by a dielectric region material, for example, ferroelectric one. The first conductive region of each MOS transistor is connected to the first plate of a respective capacitor, the second conductive region of each MOS transistor is connected to a respective bit line, the control electrode of each MOS transistor is connected to a respective word line, the second plate of each capacitor is connected to a respective plate line. The plate lines run perpendicular to the bit line and parallel to the word lines. At least two cells adjacent in a parallel direction to the bit lines share the same dielectric region material and the same plate line. In this way, the manufacturing process is not critical and the size of the cells is minimal.

Abstract translation: 层叠型电池单元包括形成在半导体材料的衬底的有源区和形成在有源区上方的电容器的MOS晶体管; 每个MOS晶体管具有第一和第二导电区域和控制电极，并且每个电容器具有由电介质区域材料（例如铁电体）隔开的第一和第二板。 每个MOS晶体管的第一导电区域连接到相应电容器的第一板，每个MOS晶体管的第二导电区域连接到相应的位线，每个MOS晶体管的控制电极连接到相应的字线， 每个电容器的第二板连接到相应的板线。 平板线垂直于位线延伸并平行于字线。 在与位线的平行方向上相邻的至少两个单元共享相同的介电区材料和相同的板线。 以这种方式，制造过程不是关键的，并且电池的尺寸是最小的。

公开(公告)号：US06511874B2

公开(公告)日：2003-01-28

申请号：US09912638

申请日：2001-07-24

Applicant: Raffaele Zambrano

Inventor： Raffaele Zambrano

IPC: H01L218242

CPC classification number: H01L27/11502 ,  H01L27/1085

Abstract: A circuit structure for semiconductor devices which are integrated on a semiconductor layer is provided. The structure comprises at least one MOS device and at least one capacitor element that has a bottom and a top electrode. The MOS device has conduction terminals formed in the semiconductor layer, as well as a control terminal covered with an overlying insulating layer of unreflowed oxide. The capacitor element is formed on the unreflowed oxide layer.

Abstract translation: 提供集成在半导体层上的半导体器件的电路结构。 该结构包括至少一个MOS器件和具有底部电极和顶部电极的至少一个电容器元件。 MOS器件具有形成在半导体层中的导电端子，以及覆盖有未溢出氧化物的上覆绝缘层的控制端子。 电容器元件形成在未流动的氧化物层上。

公开(公告)号：US06410404B1

公开(公告)日：2002-06-25

申请号：US09561272

申请日：2000-04-28

Applicant: Raffaele Zambrano

Inventor： Raffaele Zambrano

IPC: H01L2176

CPC classification number: H01L21/76264 ,  H01L21/76248 ,  H01L21/76278

Abstract: Presented is a process for manufacturing circuit structures of the SOI type integrated on a semiconductor substrate having a first type of conductivity. The process includes forming at least one well with a second type of conductivity in the semiconductor substrate and forming a hole within the well. The hole is then coated with an insulating coating layer, and an opening is formed through the insulating coating layer at the bottom of the hole. The hole is then filled with an epitaxial layer grown from a seed that was made accessible through the opening in the hole.

Abstract translation: 本发明提供一种用于制造集成在具有第一类导电性的半导体衬底上的SOI型电路结构的工艺。 该方法包括在半导体衬底中形成具有第二类导电性的至少一个阱并在阱内形成一个孔。 然后用绝缘涂层涂覆孔，并且通过孔底部的绝缘涂层形成开口。 然后将孔从由种子开始生长的外延层填充，所述外延层可通过孔中的开口接近。

公开(公告)号：US06222232B1

公开(公告)日：2001-04-24

申请号：US08886836

申请日：1997-07-01

Applicant: Angelo Magri' ,  Raffaele Zambrano ,  Ferruccio Frisina

Inventor： Angelo Magri' ,  Raffaele Zambrano ,  Ferruccio Frisina

IPC: H01L2974

CPC classification number: H01L29/7802 ,  H01L29/0611 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66712

Abstract: A MOS technology power device comprises a semiconductor substrate, a semiconductor layer of a first conductivity type superimposed over the semiconductor substrate, an insulated gate layer covering the semiconductor layer, a plurality of substantially rectilinear elongated openings parallel to each other in the insulated gate layer, a respective plurality of elongated body stripes of a second conductivity type formed in the semiconductor layer under the elongated openings, source regions of the first conductivity type included in the body stripes and a metal layer covering the insulated gate layer and contacting the body stripes and the source regions through the elongated openings. Each body stripe comprises first portions substantially aligned with a first edge of the respective elongated opening and extending under a second edge of the elongated opening to form a channel region, each first portion including a source region extending substantially from a longitudinal axis of symmetry of the respective elongated opening to the second edge of the elongated opening, and second portions, longitudinally intercalated with the first portions, substantially aligned with the second edge of the elongated opening and extending under the first edge of the elongated opening to form a channel region, each second portion including a source region extending substantially from the longitudinal axis of symmetry to the first edge of the elongated opening, the first portions and second portions of the body stripes being respectively aligned in a direction transversal to the longitudinal axis.

Abstract translation: MOS技术功率器件包括半导体衬底，叠加在半导体衬底上的第一导电类型的半导体层，覆盖半导体层的绝缘栅极层，在绝缘栅极层中彼此平行的多个基本上直线的细长开口， 形成在细长开口下方的半导体层中的相应的多个细长体条带，包括在主体条中的第一导电类型的源极区域和覆盖绝缘栅极层的金属层并接触主体条纹和 源区域通过细长的开口。 每个主体条带包括基本上与相应细长开口的第一边缘对准的第一部分，并且在细长开口的第二边缘下方延伸以形成通道区域，每个第一部分包括基本上从纵向对称轴线延伸的源区域 与细长开口的第二边缘相对的细长开口，以及纵向插入第一部分的第二部分，基本上与细长开口的第二边缘对准，并在细长开口的第一边缘下方延伸以形成通道区域， 第二部分包括基本上从纵向对称轴延伸到细长开口的第一边缘的源区域，主体条纹的第一部分和第二部分分别在与纵轴相交的方向上对齐。

公开(公告)号：US06218706B1

公开(公告)日：2001-04-17

申请号：US09418850

申请日：1999-10-15

Applicant: Charles D. Waggoner ,  Antonio Imbruglia ,  Raffaele Zambrano

Inventor： Charles D. Waggoner ,  Antonio Imbruglia ,  Raffaele Zambrano

IPC: H01L2362

CPC classification number: H01L27/0251 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An MOS integrated circuit device with improved electrostatic protection capability includes high and low voltage rails for bringing externally-supplied power to points within the chip. Input bonding pads communicate input signals to the chip from external sources. Clamping circuitry connected to the input bonding pads clamps the input bonding pads to the low voltage rail during an electrostatic discharge event appearing on the input bonding pads. A receiver circuit is coupled to each input bonding pad. Each receiver circuit has a receiver input node, a receiver output node, and overvoltage-sensitive MOS circuitry between the input and output nodes. A conductor connects each input bonding pad to its receiver circuit. The conductor has a length greater than the distance between the input bonding pad and its receiver circuit. The conductor has an inductance sufficient to prevent high frequency components of ESD events received at an input bonding pad from reaching its receiver circuit. The conductor includes at least one fold for extending the length of the conductor to exceed the distance between the input bonding pad and the receiver input node.

Abstract translation: 具有改进的静电保护能力的MOS集成电路器件包括用于将外部供电的电源带到芯片内的高低压轨道。 输入接合焊盘从外部来源传送输入信号到芯片。 连接到输入接合焊盘的夹紧电路在输入接合焊盘出现静电放电事件期间将输入接合焊盘夹紧到低压轨道。 接收器电路耦合到每个输入接合焊盘。 每个接收器电路在输入和输出节点之间具有接收器输入节点，接收器输出节点和过电压敏感MOS电路。 导体将每个输入接合焊盘连接到其接收器电路。 导体的长度大于输入接合焊盘及其接收器电路之间的距离。 导体具有足以防止在输入接合焊盘处接收的ESD事件的高频分量到达其接收器电路的电感。 导体包括至少一个折叠，用于延长导体的长度以超过输入接合焊盘和接收器输入节点之间的距离。

公开(公告)号：US5936298A

公开(公告)日：1999-08-10

申请号：US761185

申请日：1996-12-06

Applicant: Piero Capocelli ,  Raffaele Zambrano ,  Federico Pio ,  Carlo Riva

Inventor： Piero Capocelli ,  Raffaele Zambrano ,  Federico Pio ,  Carlo Riva

IPC: H01F17/00 ,  H01F41/04 ,  H01L23/522 ,  H01L29/00

CPC classification number: H01F41/046 ,  H01F17/0033 ,  H01L23/5227 ,  H01F2017/0086 ,  H01L2924/0002

Abstract: Inductive structures make highly efficient use of the magnetic flux generd, and are consistent with integrated circuit manufacturing techniques. The structures include electrically conductive layers and interconnecting conductor filled vias to define a helical winding surrounding a closed magnetic core. The magnetic core may also be formed by semiconductor manufacturing techinuqes. A method of making the structures on a semiconductor substrate concurrently with the formation of the integrated circuit itself is also disclosed.

Abstract translation: 感应结构高效地利用所产生的磁通量，并与集成电路制造技术保持一致。 这些结构包括导电层和互连导体填充的通孔，以限定围绕封闭磁芯的螺旋绕组。 磁芯也可以由半导体制造技术形成。 还公开了与形成集成电路本身同时在半导体衬底上制造结构的方法。

公开(公告)号：US5654225A

公开(公告)日：1997-08-05

申请号：US473792

申请日：1995-06-07

Applicant: Raffaele Zambrano

Inventor： Raffaele Zambrano

IPC: H01L27/04 ,  H01L21/822 ,  H01L27/02 ,  H01L27/06 ,  H01L29/78 ,  H01L21/265 ,  H01L21/70 ,  H01L27/00

CPC classification number: H01L29/7817 ,  H01L27/0255 ,  H01L29/66681 ,  H01L29/7818 ,  H01L29/782 ,  H01L29/1095 ,  H01L2924/0002

Abstract: An integrated structure active clamp for the protection of a power device against overvoltages includes a plurality of serially connected diodes, each having a first and a second electrode, obtained in a lightly doped epitaxial layer of a first conductivity type in which the power device is also obtained; a first diode of said plurality of diodes has the first electrode connected to a gate layer of the power device and the second electrode connected to the second electrode of at least one second diode of the plurality whose first electrode is connected to a drain region of the power device; said first diode has its first electrode comprising a heavily doped contact region of the first conductivity type included in a lightly doped epitaxial layer region of the first conductivity type which is isolated from said lightly doped epitaxial layer by a buried region of a second conductivity type and by a heavily doped annular region of the second conductivity type extending from a semiconductor top surface to said buried region.

Abstract translation: 用于保护功率器件免于过电压的集成结构有源钳位包括多个串联连接的二极管，每个二极管具有第一和第二电极，其在第一导电类型的轻掺杂外延层中获得，其中功率器件也是 获得; 所述多个二极管的第一二极管具有连接到功率器件的栅极层的第一电极，并且第二电极连接到多个第二电极的至少一个第二二极管的第二电极，其第一电极连接到漏极区域 电源设备; 所述第一二极管具有包括第一导电类型的重掺杂接触区域的第一电极，所述第一导电类型的重掺杂接触区域包括在第一导电类型的轻掺杂外延层区域中，该区域通过第二导电类型的掩埋区域与所述轻掺杂外延层隔离， 通过从半导体顶表面延伸到所述掩埋区域的第二导电类型的重掺杂环形区域。

公开(公告)号：US5523607A

公开(公告)日：1996-06-04

申请号：US383213

申请日：1995-02-02

Applicant: Raffaele Zambrano

Inventor： Raffaele Zambrano

IPC: H01L21/331 ,  H01L27/06 ,  H01L29/735 ,  H01L29/70 ,  H01L29/78 ,  H01L29/50

CPC classification number: H01L29/6625 ,  H01L27/0623 ,  H01L29/735

Abstract: A bipolar control transistor, forming part of an integrated current-limiter device comprises inside an epitaxial layer superimposed over a semiconductor substrate of a first type of conductivity, a base region of a second type of conductivity accessible from a base contact and regions of collector and emitter of the first type of conductivity contained in the base region and accessible from respective collector and emitter contacts. The base region comprises at least one highly-doped deep-body region which contains almost completely said emitter region, a lightly-doped body region which contains the collector region and an intermediate-doped region which co-operates with the first deep-body region to completely contain the emitter region and a surface area of the base region that is included between the regions of collector and emitter. There is also at least one first portion of a layer of polysilicon superimposed and self-aligned with the surface area between the regions of collector and emitter and electrically connected to the collector contact of the bipolar transistor.

公开(公告)号：US5500551A

公开(公告)日：1996-03-19

申请号：US273589

申请日：1994-07-11

Applicant: Santo Puzzolo ,  Raffaele Zambrano ,  Mario Paparo

Inventor： Santo Puzzolo ,  Raffaele Zambrano ,  Mario Paparo

IPC: H01L21/8249 ,  H01L21/331 ,  H01L21/8222 ,  H01L27/06 ,  H01L27/082 ,  H01L29/73 ,  H01L29/732 ,  H01L29/00

CPC classification number: H01L27/0823 ,  H01L21/8222 ,  H01L27/0825

Abstract: A bipolar power transistor and a low voltage bipolar transistor are combined in an emitter switching or a semibridge configuration in an integrated structure. In a version with non-isolated components, the components of the structure are totally or partially superimposed on each other, partly in a first epitaxial layer and partly in a second epitaxial layer, and the low voltage bipolar transistor is situated above the emitter region of the bipolar power transistor which is thus a completely buried active structure. In a version with isolated components, there are two P+ regions in an N- epitaxial layer. The first P+ region constitutes the power transistor base and encloses the N+ emitter region of the power transistor. The second P+ region encloses two N+ regions and one P+ region, constituting the collector, emitter, and base regions respectively of the low voltage transistor. A metallization on the front of the chip provides a connection between the collector contact of the low voltage transistor and the emitter contact of the power transistor.

Abstract translation: 双极功率晶体管和低电压双极晶体管以集成结构组合在发射极开关或半谐振器配置中。 在具有非隔离部件的版本中，结构的部件彼此完全或部分地叠置，部分地在第一外延层中，部分地叠置在第二外延层中，并且低电压双极晶体管位于 双极功率晶体管因此是完全埋入的有源结构。 在具有隔离元件的版本中，在N外延层中有两个P +区。 第一P +区域构成功率晶体管基极并且包围功率晶体管的N +发射极区域。 第二P +区域包围分别构成低压晶体管的集电极，发射极和基极区域的两个N +区域和一个P +区域。 芯片前面的金属化提供了低压晶体管的集电极触点和功率晶体管的发射极触点之间的连接。

公开(公告)号：US5426320A

公开(公告)日：1995-06-20

申请号：US225147

申请日：1994-04-08

Applicant: Raffaele Zambrano

Inventor： Raffaele Zambrano

IPC: H01L29/78 ,  H01L27/02 ,  H01L27/04 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L27/0255 ,  H01L29/7802

Abstract: An integrated structure protection device suitable for protecting a power MOS device from electrostatic discharges comprises a junction diode comprising a first electrode made of a highly doped region of a first conductivity type surrounded by a body region of a second conductivity type and representing a second electrode of the junction diode, which in turn is surrounded by a highly doped deep body region of said second conductivity type. The highly doped region is connected to a polysilicon gate layer representing the gate of the power MOS device, while the deep body region is connected to a source region of the power MOS.

Abstract translation: 适用于保护功率MOS器件免受静电放电的集成结构保护装置包括结二极管，其包括由第一导电类型的高掺杂区域构成的第一电极，该第一电极由第二导电类型的体区包围， 结二极管，其又由所述第二导电类型的高掺杂深体区域包围。 高掺杂区域连接到表示功率MOS器件的栅极的多晶硅栅极层，而深体区域连接到功率MOS的源极区域。