发明授权
- 专利标题: Testability architecture and techniques for programmable interconnect architecture
- 专利标题(中): 可测试架构和可编程互连架构技术
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申请号: US102381申请日: 1993-08-05
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公开(公告)号: US5432441A公开(公告)日: 1995-07-11
- 发明人: Khaled A. El-Ayat , Jia-Hwang Chang
- 申请人: Khaled A. El-Ayat , Jia-Hwang Chang
- 申请人地址: CA Sunnyvale
- 专利权人: Actel Corporation
- 当前专利权人: Actel Corporation
- 当前专利权人地址: CA Sunnyvale
- 主分类号: G01R31/28
- IPC分类号: G01R31/28 ; G01R31/3185 ; H03K19/177 ; G01R31/02
摘要:
In an integrated circuit having a plurality of function modules, each of the function modules having at least two inputs and at least one output. The integrated circuit is user programmable such that interconnections between selected ones of the function modules and input/output pins on the integrated circuit may be made. The integrated circuit further having two states, a first unprogrammed state where none of the interconnections have been made, and a second, programmed state in which selected interconnections have been made. Circuitry for testing the functionality of individual ones of the function modules when the integrated circuit is in the unprogrammed state comprises addressing means for selecting any one of the function modules, data input means for providing a selected logic level to at least one of the inputs of the function module selected by the addressing means, and output-connecting means, responsive to the addressing means, for temporarily connecting the output of the selected one of the function modules to one of the input/output pins on the integrated circuit.
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