A system and method for connecting a short word length memory to a significantly wider bus operated in an address/data multiplexing mode. A mode of operation is defined for the bus whereby the bus lines are divided for purposes of memory accessing into a data group and an address group. The data group is operable bidirectionally to read or write memory, using the addresses provided on the group of address lines. This architecture and practice is particularly suited for a boot ROM used with processors, in that such ROMs are normally of relatively short word length while the processors are of relatively long word length and are accordingly connected to buses of similar long word length. Bridge logic interfaces the processor bus to the ROM for sequencing, timing and supplemental control in converting the data from the ROM format to the processor format.