公开(公告)号：US20090144503A1

公开(公告)日：2009-06-04

申请号：US11949935

申请日：2007-12-04

申请人： Marc R. Faucher ,  Hillery C. Hunter ,  William R. Reohr ,  Peter A. Sandon ,  Vijayalakshmi Srinivasan ,  Arnold S. Tran

发明人： Marc R. Faucher ,  Hillery C. Hunter ,  William R. Reohr ,  Peter A. Sandon ,  Vijayalakshmi Srinivasan ,  Arnold S. Tran

IPC分类号： G06F12/00

CPC分类号： G06F12/0893 ,  G06F12/0864 ,  G06F12/123

摘要： A method of integrating a hybrid architecture in a set associative cache having a first type of memory structure for one or more ways in each congruence class, and a second type of memory structure for the remaining ways of the congruence class, includes determining whether a memory access request results in a cache hit or a cache miss; in the event of a cache miss, determining whether LRU way of the first type memory structure is also the LRU way of the entire congruence class, and if not, then copying the contents of the LRU way of the first type memory structure into the LRU way of the entire congruence class, and filling the LRU way of the first type memory structure with a new cache line in the event of a cache miss; and updating LRU bits, depending upon the results of the memory access request.

摘要翻译： 一种将混合体系结构集成在具有第一类型的存储器结构的集合关联高速缓存中的方法，所述第一类型的存储器结构用于每个同余类中的一种或多种方式，以及用于所述一致类的剩余方式的第二类型的存储器结构，包括确定存储器 访问请求导致缓存命中或缓存未命中; 在高速缓存未命中的情况下，确定第一类型存储器结构的LRU方式是否也是整个同余类的LRU方式，如果不是，则将第一类型存储器结构的LRU方式的内容复制到LRU中 并且在缓存未命中的情况下用新的高速缓存行填充第一类型存储器结构的LRU方式; 并根据存储器访问请求的结果更新LRU位。

公开(公告)号：US20080313339A1

公开(公告)日：2008-12-18

申请号：US12191336

申请日：2008-08-14

申请人： Marc R. Faucher ,  Christos J. Georgiou ,  Ann Marie Rincon

发明人： Marc R. Faucher ,  Christos J. Georgiou ,  Ann Marie Rincon

IPC分类号： G06F15/16

CPC分类号： G06F13/385 ,  G06F12/0875 ,  G06F12/122 ,  H04L49/90 ,  H04L67/14 ,  H04L69/28

摘要： The invention provides a method, system, and program product for managing a connection. In particular, the invention manages connection information in memory based on an expected usage of the corresponding connection. Connection information can be stored in faster memory, such as cache memory, when the connection is expected to have numerous additional messages. Similarly, the connection information for a connection not expected to have many additional messages can be swapped out of the cache memory and stored in relatively slower memory. As a result, the connection information that is more frequently used is more likely to be available in a faster memory.

摘要翻译： 本发明提供了一种用于管理连接的方法，系统和程序产品。 特别地，本发明基于相应连接的预期使用来管理存储器中的连接信息。 连接信息可以存储在较快的存储器中，如缓存存储器，当连接预期有大量附加消息时。 类似地，不期望具有许多附加消息的连接的连接信息可以从高速缓存存储器中交换并存储在相对较慢的存储器中。 因此，更频繁使用的连接信息更有可能在更快的存储器中可用。

公开(公告)号：US06532520B1

公开(公告)日：2003-03-11

申请号：US09394965

申请日：1999-09-10

申请人： Alvar A. Dean ,  Marc R. Faucher ,  John W. Goetz ,  Kenneth J. Goodnow ,  Paul T. Gutwin ,  Stephen W. Mahin ,  Wilbur D. Pricer

发明人： Alvar A. Dean ,  Marc R. Faucher ,  John W. Goetz ,  Kenneth J. Goodnow ,  Paul T. Gutwin ,  Stephen W. Mahin ,  Wilbur D. Pricer

IPC分类号： G06F1200

CPC分类号： G06F12/121 ,  G06F12/127 ,  G06F2212/1021 ,  G06F2212/6042

摘要： A method and apparatus are provided for managing cache allocation for a plurality of data types in a unified cache having dynamically allocable lines for first type data and for second type data. Cache allocation is managed by counting misses to first type data and misses to second type data in the unified cache, and by determining when a difference between a number of first type data misses and a number of second type data misses crosses a preselected threshold. A replacement algorithm of the unified cache then is adjusted in response to the detected crossing of the preselected threshold, the adjusting step including increasing a replacement priority of the first type data lines in the cache. The replacement algorithm preferably is an LRU algorithm wherein the adjusting step includes incrementing an age indication of the first type data lines. Hardware for implementing the inventive cache allocation management method comprises a miss counter configured to increment its count in response to a miss to first type data signal on a first counter input and to output a first logic state on a first counter output when the counter's count exceeds a first predetermined count. A priority adjustment circuit coupled to the first counter output increases the replacement priority of the first type data relative to the replacement priority of the second type data in response to the first logic state output by the miss counter.

摘要翻译： 提供了一种方法和装置，用于管理具有用于第一类型数据和第二类型数据的动态可分配行的统一高速缓存中的多个数据类型的高速缓存分配。 高速缓存分配通过对统一高速缓存中的第一类型数据和第二类型数据的丢失进行计数，并且通过确定多个第一类型数据丢失与多个第二类型数据丢失之间的差异何时穿过预选阈值来管理高速缓存分配。 然后，响应于检测到的预选阈值的交叉，调整统一高速缓存的替换算法，该调整步骤包括增加高速缓存中的第一类型数据线的替换优先级。 替换算法优选地是LRU算法，其中调整步骤包括递增第一类型数据线的年龄指示。 用于实现本发明的高速缓存分配管理方法的硬件包括错误计数器，其配置为响应于第一计数器输入上的第一类型数据信号的未命中而增加其计数，并且当计数器的计数超过时，在第一计数器输出上输出第一逻辑状态 第一预定计数。 耦合到第一计数器输出的优先级调整电路响应于未命中计数器输出的第一逻辑状态，增加第一类型数据相对于第二类型数据的替换优先级的替换优先级。

公开(公告)号：US6108730A

公开(公告)日：2000-08-22

申请号：US32448

申请日：1998-02-27

申请人： Timothy J. Dell ,  Kent A. Dramstad ,  Marc R. Faucher ,  Bruce G. Hazelzet

发明人： Timothy J. Dell ,  Kent A. Dramstad ,  Marc R. Faucher ,  Bruce G. Hazelzet

IPC分类号： G06F13/14 ,  G11C29/00

CPC分类号： G06F13/14 ,  G06F11/10 ,  G11C5/02 ,  G11C2029/0411 ,  G11C5/04

摘要： A memory card adapter and method is provided which can add features or provide functions to a computer system's memory modules without having to replace and discard existing memory modules. An adapter is provided which has electrical contacts that are capable of being plugged into a memory module receiving socket of a motherboard and a memory module receiving socket capable of receiving and retaining a memory module such as a SIMM. The adapter has logic, circuitry and/or memory chips to add new function to the existing memory module and also has all information and hardware needed for proper interface with the motherboard of the computer system. The present invention can add a variety of function such as parity, error correction code and error correction code on SIMM as well as convert signals which form from the system for use on the SIMM which signals in the form generate by the computer are not compatible with the SIMM.

摘要翻译： 提供了一种存储卡适配器和方法，其可以向计算机系统的存储器模块添加功能或提供功能，而无需更换和丢弃现有的存储器模块。 提供了一种适配器，其具有能够插入主板的存储器模块接收插座的电触点和能够接收和保持诸如SIMM的存储器模块的存储器模块接收插座。 该适配器具有逻辑，电路和/或存储器芯片，以便为现有存储器模块增加新功能，并且还具有与计算机系统的主板正确接口所需的所有信息和硬件。 本发明可以在SIMM上添加诸如奇偶校验，纠错码和纠错码的各种功能，以及从系统中形成的用于在SIMM上使用的信号，由计算机生成的形式的信号不兼容 SIMM。

公开(公告)号：US08244880B2

公开(公告)日：2012-08-14

申请号：US12191336

申请日：2008-08-14

申请人： Marc R. Faucher ,  Christos J. Georgiou ,  Ann Marie Rincon

发明人： Marc R. Faucher ,  Christos J. Georgiou ,  Ann Marie Rincon

IPC分类号： G06F15/16

CPC分类号： G06F13/385 ,  G06F12/0875 ,  G06F12/122 ,  H04L49/90 ,  H04L67/14 ,  H04L69/28

摘要： The invention provides a method, system, and program product for managing a connection. In particular, the invention manages connection information in memory based on an expected usage of the corresponding connection. Connection information can be stored in faster memory, such as cache memory, when the connection is expected to have numerous additional messages. Similarly, the connection information for a connection not expected to have many additional messages can be swapped out of the cache memory and stored in relatively slower memory. As a result, the connection information that is more frequently used is more likely to be available in a faster memory.

摘要翻译： 本发明提供了一种用于管理连接的方法，系统和程序产品。 特别地，本发明基于相应连接的预期使用来管理存储器中的连接信息。 连接信息可以存储在较快的存储器中，如缓存存储器，当连接预期有大量附加消息时。 类似地，不期望具有许多附加消息的连接的连接信息可以从高速缓存存储器中交换并存储在相对较慢的存储器中。 因此，更频繁使用的连接信息更有可能在更快的存储器中可用。

公开(公告)号：US07865694B2

公开(公告)日：2011-01-04

申请号：US11382967

申请日：2006-05-12

申请人： Kerry Bernstein ,  Timothy J. Dalton ,  Marc R. Faucher ,  Peter A. Sandon

发明人： Kerry Bernstein ,  Timothy J. Dalton ,  Marc R. Faucher ,  Peter A. Sandon

IPC分类号： G06F15/76

CPC分类号： H01L25/0652 ,  H01L25/18 ,  H01L2225/06562 ,  H01L2924/0002 ,  H01L2924/00

摘要： A multi-layer silicon stack architecture includes one or more processing layers including one or more computing elements; one or more networking layers disposed between the processing layers, the network layer includes one or more networking elements, wherein each computing element includes a plurality of network connections to adjacently disposed networking elements.

摘要翻译： 多层硅堆栈架构包括一个或多个包括一个或多个计算元件的处理层; 布置在处理层之间的一个或多个网络层，网络层包括一个或多个网络元件，其中每个计算元件包括到相邻布置的网络元件的多个网络连接。

公开(公告)号：US6052818A

公开(公告)日：2000-04-18

申请号：US32153

申请日：1998-02-27

申请人： Timothy J. Dell ,  Marc R. Faucher ,  Bruce G. Hazelzet

发明人： Timothy J. Dell ,  Marc R. Faucher ,  Bruce G. Hazelzet

IPC分类号： G06F11/10 ,  H04L1/00

CPC分类号： H04L1/0057 ,  G06F11/10 ,  G06F11/1048

摘要： An apparatus and method in which ECC bus protection capability can be generated on a memory card in conjunction with a computer system with a built-in ECC capability to reduce data transmission errors. Data generated by the system is transmitted to the card and stored in DRAMs. On a read cycle, the card generates a set of checkbits which are sent to the system on a checkbit bus. The system generates a set of checkbits from the data read from the memory card and compares these checkbits with those received from the memory card. A mismatch indicates transmission error on the bus(s) during a read cycle. Any correctable error is corrected. Data is invalidated if an uncorrectable error is detected. In another embodiment checkbits generated by the system during a write cycle are transmitted to the card an checkbits are generated by the card. These two sets of checkbits are compared and if there is a mismatch data is either flagged as bad or corrected. Furthermore, in one embodiment, if the memory card does "not know" in advance the type of ECC or H-matrix code resident in the computer system, the card has the capability to determine what H-matrix code is resident and set up a corresponding H-matrix.

摘要翻译： 结合具有内置ECC能力的计算机系统，可以在存储卡上产生ECC总线保护能力以减少数据传输错误的装置和方法。 由系统产生的数据被发送到卡并存储在DRAM中。 在读取周期中，卡生成一组在checkbit总线上发送到系统的校验位。 该系统根据从存储卡读取的数据生成一组校验码，并将这些校验码与从存储卡接收的数据进行比较。 不匹配在读取周期中指示总线上的传输错误。 任何可纠正的错误得到纠正。 如果检测到无法纠正的错误，则数据无效。 在另一个实施例中，由系统在写入周期期间生成的校验码被发送到卡，由卡产生一个校验位。 将这两组校验比较，如果存在不匹配数据被标记为坏或校正。 此外，在一个实施例中，如果存储卡事先“不知道”驻留在计算机系统中的ECC或H矩阵代码的类型，则该卡具有确定什么H矩阵代码驻留并建立一个 相应的H矩阵。

公开(公告)号：US5969997A

公开(公告)日：1999-10-19

申请号：US942825

申请日：1997-10-02

申请人： Michael P. Clinton ,  Marc R. Faucher ,  Erik L. Hedberg ,  Mark W. Kellogg ,  Wilbur D. Pricer

发明人： Michael P. Clinton ,  Marc R. Faucher ,  Erik L. Hedberg ,  Mark W. Kellogg ,  Wilbur D. Pricer

IPC分类号： G11C11/41 ,  G11C11/401 ,  G11C11/407 ,  G11C11/409 ,  G11C15/00

CPC分类号： G11C11/409 ,  G11C11/407

摘要： A high speed Random Access Memory (RAM) array device includes several logical banks, each of which can be uniquely addressed. Each of these logical banks contains a unique memory array segment and associated page register, the latter serving as a temporary storage location during high-speed page hit operations. To reduce latency during an initial page hit, further array optimization is realized by segmenting each logical bank into two segments with one, smaller segment, comprising a faster random access memory (FRAM) for storing initial data in a data stream. A high speed page register connects the FRAM directly to a multiplexer/demultiplexer connected to the device I/O ports bypassing an internal bus protocol such that the initial data can be transferred between the FRAM and the I/O ports faster thereby improving page-hit latency. Hence, segmenting the logical banks to include only a small high speed segment results in a performance gain approaching what could be achieved by implementing the entire memory device with a high speed FRAM, but at much lower cost.

摘要翻译： 高速随机存取存储器（RAM）阵列器件包括几个逻辑存储体，每个逻辑存储体可以被唯一地寻址。 这些逻辑组中的每一个包含唯一的存储器阵列段和相关联的页寄存器，后者在高速页命中操作期间用作临时存储位置。 为了在初始页面命中期间减少延迟，通过将每个逻辑存储体分割成具有一个较小段的两个段来实现进一步的阵列优化，其包括用于在数据流中存储初始数据的更快的随机存取存储器（FRAM）。 高速页寄存器将FRAM直接连接到绕过内部总线协议的设备I / O端口连接的多路复用器/解复用器，从而可以更快地在FRAM和I / O端口之间传输初始数据，从而提高页命中率 潜伏。 因此，将逻辑存储体分割为仅包含小的高速段导致通过以高速FRAM实现整个存储器件而可以以低得多的成本实现可达到的性能增益。

公开(公告)号：US5959845A

公开(公告)日：1999-09-28

申请号：US933216

申请日：1997-09-18

申请人： Marc R. Faucher

发明人： Marc R. Faucher

IPC分类号： H05K1/00 ,  H05K1/11 ,  H05K1/18 ,  H05K7/02

CPC分类号： H05K1/181 ,  H05K1/0295 ,  H05K1/111 ,  H05K2201/09954 ,  H05K2201/10515 ,  H05K2201/10704 ,  H05K2201/10734 ,  Y02P70/611

摘要： A circuit board for receiving different chip modules at each chip module site has a site for receiving a chip module having electrical connectors thereon and a first set of contacts at the chip module site having a first arrangement for receiving a chip module having an electrical connector footprint conforming to the first module contact arrangement. There is also provided a second set of contacts at the chip module site having a second arrangement for receiving a chip module having an electrical connector footprint conforming to the second module contact arrangement, the second set of contacts having a different arrangement than, and being electrically connected to, the first set of contacts.

摘要翻译： 用于在每个芯片模块位置处接收不同芯片模块的电路板具有用于接收其上具有电连接器的芯片模块的位置，并且在芯片模块位置处的第一组触点具有用于接收具有电连接器覆盖区的芯片模块的第一布置 符合第一个模块接触装置。 还提供了在芯片模块位置处的第二组触点，其具有用于接收具有符合第二模块接触装置的电连接器覆盖区的芯片模块的第二布置，第二组触点具有不同的布置，并且是电 连接到第一套联系人。

公开(公告)号：US5448521A

公开(公告)日：1995-09-05

申请号：US157487

申请日：1993-11-12

申请人： Sean E. Curry ,  Mark E. Dean ,  Marc R. Faucher ,  James C. Peterson ,  Howard C. Tanner

发明人： Sean E. Curry ,  Mark E. Dean ,  Marc R. Faucher ,  James C. Peterson ,  Howard C. Tanner

IPC分类号： G06F12/06 ,  G06F12/00 ,  G06F13/36 ,  G06F13/40 ,  G11C8/00

CPC分类号： G06F13/4018

摘要： A system and method for connecting a short word length memory to a significantly wider bus operated in an address/data multiplexing mode. A mode of operation is defined for the bus whereby the bus lines are divided for purposes of memory accessing into a data group and an address group. The data group is operable bidirectionally to read or write memory, using the addresses provided on the group of address lines. This architecture and practice is particularly suited for a boot ROM used with processors, in that such ROMs are normally of relatively short word length while the processors are of relatively long word length and are accordingly connected to buses of similar long word length. Bridge logic interfaces the processor bus to the ROM for sequencing, timing and supplemental control in converting the data from the ROM format to the processor format.

摘要翻译： 一种用于将短字长存储器连接到以地址/数据复用模式操作的较宽总线的系统和方法。 为总线划分了一种操作模式，为了存储器访问数据组和地址组的目的，总线被划分。 数据组可以双向可操作地使用地址线组上提供的地址来读或写存储器。 这种架构和实践特别适合于与处理器一起使用的引导ROM，因为这样的ROM通常具有相对较短的字长，而处理器的字长度相对较长，因此连接到类似长字长的总线。 桥接逻辑将处理器总线连接到ROM，用于将数据从ROM格式转换为处理器格式进行排序，定时和补充控制。