发明授权
US5448576A Boundary scan architecture extension 失效
边界扫描架构扩展

Boundary scan architecture extension
摘要:
A method and apparatus provides improved modes of operation of a standard test bus based on a standard boundary scan architecture which minimizes the number of bits required to be serially scanned into the controllers of the various devices connected to the bus by temporarily disabling scan paths not required to be utilized. Means for continuously verifying the inoperative state of test logic and for diagnosing test logic faults are also described.
公开/授权文献
信息查询
0/0