A PCI bus writes non-contiguous data in a maximum of two PCI bus write cycles. A Bridge is provided which can combine data within its write buffer such that non-contiguous data results. Some I/O devices on the PCI bus cannot handle non-contiguous data, so the Bridge detects non-contiguous data, and generates appropriate write cycles to the PCI bus to transfer this data in a contiguous fashion. The method described takes advantage of the multiple data phase capability of the PCI bus to transfer data at more than one address during one PCI bus write cycle, and optimizes these transfers to assure that all non-contiguous transfers can occur in only two PCI bus write cycles.