发明授权
- 专利标题： Incrementing and decrementing counter circuits
- 专利标题（中）： 递增递减计数器电路
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申请号： US308460申请日： 1994-09-19
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公开(公告)号： US5467376A公开(公告)日： 1995-11-14
- 发明人: Guoliang Shou , Sunao Takatori , Makoto Yamamoto
- 申请人： Guoliang Shou , Sunao Takatori , Makoto Yamamoto
- 申请人地址： JPX Tokyo JPX Tokyo
- 专利权人： Yozan Inc.,Sharp Corporation
- 当前专利权人： Yozan Inc.,Sharp Corporation
- 当前专利权人地址： JPX Tokyo JPX Tokyo
- 优先权： JPX5-256377 19930920; JPX5-256530 19930920
- 主分类号： G06F7/50
- IPC分类号： G06F7/50 ; G06F7/505 ; H03K25/00
摘要：
A counter circuit converts a full count to a zero count and a zero count to a full count. An incrementing counter circuit according to the present invention has a plurality of threshold circuits with stepwise thresholds. An output of the highest threshold circuit is used as a cut off signal for other threshold circuits. A decrementing counter circuit according to the present invention has a plurality of threshold circuits from the lowest threshold to the highest thresholds. An output of the lowest threshold circuit is used as a closing signal for other threshold circuits.
公开/授权文献
- US4955558A Reaction control system 公开/授权日：1990-09-11
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